This thesis presents the main properties and the implementation of a three stage pipelined RISC processor called s816 in SystemVerilog. S816 has been developed within ON Semiconductor for use in signal processing systems. It contains 79 instructions that allow the processor to be used for specific tasks in the field of signal processing and for use in more general-purpose systems, which require a CPU. Hardware logic of s816 contains special modules for shifting, adding, multiplying and dividing, which were implemented in a way that achieve a compromise between logic size, speed and design complexity. S816 uses QMEM bus, which has Slovenian roots, and is a representative of Harvard processor architecture. In addition to processor hardware an assembler and compiler for s816 have also been developed. This thesis also explains the use of a C++ processor simulator, which serves as a flexible software simulation of hardware logic. Internal verification of s816 is described, which encompasses the use of hardware SystemVerilog simulation, C++ simulator, SystemVerilog coverage mechanisms and scripts that connect and take care of processor verification flow.