Zasnova in verifikacija procesorja za obdelavo signalov

MUROVIČ, TADEJ (avtor), Trost, Andrej (mentor)

Magistrsko delo predstavi lastnosti in implementacijo tristopenjsko cevljenega RISC-procesorja, imenovanega s816, v strojno opisnem jeziku SystemVerilog. Procesor je bil razvit v okviru podjetja ON Semiconductor za uporabo v sistemih za obdelavo signalov. Vsebuje 79 ukazov, ki omogočajo uporabo procesorja za specifične naloge v svetu obdelave signalov in za uporabo v splošno namenskih sistemih, kjer se potrebuje CPE. Strojna logika procesorja ima posebne module za pomikanje, seštevanje, množenje in deljenje, ki so bili implementirani na način, ki dosega kompromis med prostorsko zasedenostjo, hitrostjo in zahtevnostjo dizajna. Procesor uporablja QMEM-vodilo slovenskih korenin in je predstavnik harvardske arhitekture. Magistrsko delo obsega tudi opis programskega dela procesorja. Poleg strojne implementacije sta se razvila tudi zbirnik in prevajalnik za programiranje s816 ter C++ simulator, ki služi programski simulaciji logike. V okviru verifikacijskega dela naloge je predstavljena še interna verifikacija s816, ki je sestavljena iz simulacije strojne kode, C++ simulatorja, pokritostnih mehanizmov SystemVeriloga in skript, ki povezujejo vse našteto.

• Jezik: Slovenski jezik
• Ključne besede: s816, RISC, cevljenje, CPE, SystemVerilog
• Vrsta gradiva: Magistrsko delo/naloga
• Organizacija: FE - Fakulteta za elektrotehniko
• Leto izida: 2017
• PID: 20.500.12556/RUL-92378
• Datum objave v RUL: 26.05.2017

Sekundarni jezik

• Jezik: Angleški jezik
• Naslov: Design and verification of digital signal processor

Izvleček

This thesis presents the main properties and the implementation of a three stage pipelined RISC processor called s816 in SystemVerilog. S816 has been developed within ON Semiconductor for use in signal processing systems. It contains 79 instructions that allow the processor to be used for specific tasks in the field of signal processing and for use in more general-purpose systems, which require a CPU. Hardware logic of s816 contains special modules for shifting, adding, multiplying and dividing, which were implemented in a way that achieve a compromise between logic size, speed and design complexity. S816 uses QMEM bus, which has Slovenian roots, and is a representative of Harvard processor architecture. In addition to processor hardware an assembler and compiler for s816 have also been developed. This thesis also explains the use of a C++ processor simulator, which serves as a flexible software simulation of hardware logic. Internal verification of s816 is described, which encompasses the use of hardware SystemVerilog simulation, C++ simulator, SystemVerilog coverage mechanisms and scripts that connect and take care of processor verification flow.

• Ključne besede: s816, RISC, pipeline, CPU, SystemVerilog