This work presents the design of a QoS system intended to improve service quality and connection reliability in Ethernet networks, particularly in situations where the incoming traffic exceeds the capacity of the outgoing channel. In such cases, various forms of network performance degradation may occur: from mild deterioration of connection quality, such as increased latency or throughput fluctuations, to complete loss of connectivity. The latter can be especially critical in environments that handle traffic of vital importance—such as industrial control systems, banking networks, or security institutions—where even brief interruptions can lead to severe consequences.
The presented QoS system is based on well-established and thoroughly tested traffic-management algorithms that enable control over buffer occupancy, fair bandwidth allocation, and prevention of overload conditions. The design combines the robustness of classical approaches with a modular structure that allows further upgrades and adaptations to the specific requirements of the target network environment. The result is a flexible and scalable system capable of effectively supporting both general-purpose and highly specialized applications where reliable data transmission is essential.
The system has been fully implemented on an FPGA platform, which provides a significant advantage for processing network traffic. FPGAs enable true parallel execution of logic, allowing individual system components—from buffer-occupancy monitoring to arbitration and packet dropping—to operate simultaneously without blocking one another. This approach greatly reduces latency and enables extremely high data throughput, as packet processing is performed continuously and directly in hardware. For these reasons, FPGAs are an ideal platform for implementing such mechanisms, which must operate deterministically, quickly, and reliably even at very high transmission speeds.
|
