The master's thesis focuses on the challenge of structured testing of hardware description code for FPGA logic. This is often a process that receives insufficient attention and resources during development, especially in smaller teams. The lack of a systematic approach can therefore lead to prolonged development time, additional costs and undetected errors in the long term.
The thesis begins with an analysis of the sources of errors and methods for protecting against the loss of functional versions. It continues with a presentation of the language's capabilities, an exploration of existing solutions, and relatively straightforward options for building a scalable system. UVM, identified as the most promising choice, is implemented and adapted to a real-world example of a tested structure in the final part.
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