In this work we present a continuous-time digital transmitter for high-frequency (HF) radiofrequency identification (RFID) reader. The transmitter is designed to be compatible with the latest version of the NFC Forum Analog Technical Specification [1] and EMVCo EMV Level 1 Specifications for Payment Systems Contactless Interface Specification [2]. During the research and design phase, we also aimed to be compatible with requirements presented in the standard ISO 14443, but which have not been added yet to previously mentioned specifications.
In doctoral thesis we firstly aimed to study scientific literature on the topic and to find modern solutions that are suitable for adaptation to HF RFID technologies, as there was a lack of relevant literature in the NFC RFID field. We identified continuous-time digital technology as promising for reaching our goals for transmitter power efficiency, efficient use of silicon area, and for implementing the functionalities that are required to achieve compatibility with relevant specifications. We described the concept of a continuous-time digital technology transmitter, compared it to alternative solutions that we also identified in the literature, and then highlighted the advantages of our implemented concept. The performance measured showed that our solution is compatible with NFC Forum Analog Technical Specification 2.1 with a good margin on the limits set in the specification. Our main motivation for this work were the requirements, published by NFC Forum Analog Technical Specification 2.1, which, compared to previous versions of the specification, tightened requirements for the transmitter. Yet another motivation was to improve the compatibility between NFC readers and different antennas.
In the introduction we present the basic concepts of the HF RFID and digital transmitters that are required to understand this work. We then focus on the goals and motivation of this work, where we describe the challenge of increasing requirements for transmitters due to the use of ever-smaller antennas and the advantage of digital technologies over their analog counterparts.
In the second chapter we give an overview of the outphasing operation and the relevant scientific literature in the field of digital transmitters in general and in the field of HF RFID transmitters. We present best works in the field of digital transmitters that we selected as the basis for our design. Then we present relevant works in the field of HF RFID transmitters. We note that there are very few NFC reader transmitters presented in the literature, especially compared to the amount of other literature in HF RFID and RFID in general. In the presented works, we identify the weaknesses and potential improvements, which we also incorporate into our design and use later to compare to our work.
The third chapter presents our concept for the transmitter in detail. First, we focus on presenting the structure of the transmitter and receiver in the NFC readers, where we mainly focus on the transmitter noise. Then we present the structure of our transmitter built on the basis of continuous-time digital technology. The new transmitter is composed of a digital processing unit that contains lookup tables and an interpolator as well as of an analog part that contains a phase modulator, a regulator which provides power to the D-class amplifier, and the amplifier itself. The phase modulator is a digital-to-time converter, which is designed to maximize the phase slew rate for NFC. To ensure precise phases in the digital-to-time converter, a delay-locked loop is implemented, which automatically removes the effect of any process, supply, and temperature variation. Because the phase modulator also adds some noise into the transmission path, we implemented a bypass path for the carrier signal, which contains a minimal number of elements to ensure minimum noise during reception. To ensure phase synchronization between the two paths we implemented a phase synchronizer, which, in addition to synchronizing the delay between the two paths, also corrects the modulator input clock duty cycle. This is mandatory due to the use of inverting delay cells in the modulator, which are sensitive to the input clock duty cycle.
In the fourth chapter, we first present the criteria for evaluating the performance of a transmitter in NFC. Then we show the operation of our implemented system and a method to evaluate the performance in simulation, based on criteria defined in specifications. We present the results obtained with the aforementioned method. To compare the results we present two possible alternative solutions based on our suggestion on how to upgrade one of the works in the literature. We evaluate both alternative solutions using the same method as our system and find that our system is superior not only in terms of performance, but also exhibits lower required silicon area, lower power consumption and better scalability with smaller process technologies.
The measurement setup is given in the fifth chapter. It is used to evaluate the performance of our solution implemented on a test chip. First, we perform a set of measurements using the same conditions as were used in the simulation environment and we compare the measurement results with the simulation results. We find a good correlation between the results. Then we perform a set of measurements according to NFC Forum Analog Technical Specification 2.1 and NFC Forum Test Cases for Analog 2.1 [4]. We find that the measured results exceed the minimum requirements set in the specification. Finally, we measure the phase noise of the transmitter and the total noise of the receiver, from which we calculate the transmitter noise power. We compare the noise of the newly implemented transmitter to the noise of the previous generation transmitter, which is also implemented alongside our new transmitter on the test chip. We find that the system for bypassing the modulator prevented its noise from coming into the received signal during reception, when low noise is most critical.
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