The thesis addresses the possible design of Keccak hash function for the purpose of implementation in digital circuit. The primary goal of the thesis was to develop a fully parameterized Keccak hash function module in HDL language Verilog, which would allow the user to integrate it into different systems and choose the desired properties of the module. The user should be able to select desired input bus width, number of implemented buffers and specific instance of Keccak hash function.
At the beginning of the document, general properties of cryptographic hash functions are presented, followed by the detailed description of Keccak hash function and its sponge construction. The practical part of the thesis proposes the architecture of the circuit and describes its inner working, properties and requirements that were considered while building the circuit. The final part of the thesis presents FPGA and ASIC synthesis results, as well as the analysis of the effects of mentioned parameters
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