Testiranje naprave za zbiranje blokirnih signalov

BOGATAJ, JANKO (author), Žemva, Andrej (mentor)

Simulator za testiranje naprave, ki zbira blokirne signale, je narejen v dveh izvedbah. Prva izvedba omogoča testiranje naprave na avtomatiziran način, druga pa na ročni način. Zgradba in delovanje teh dveh verzij je zelo podobna. Največjo razliko občuti uporabnik, ki uporablja uporabniški vmesnik oziroma čelno ploščo simulatorja. Napravo, ki jo želimo testirati, je potrebno priključiti na simulator preko vhodno-izhodnih priključkov FPGA kartice simulatorja, serijski port naprave pa na kontroler, kjer poteka programski del simulatorja. Simulator je implementiran v programskem okolju LabVIEW. Kako bo potekalo avtomatsko testiranje, je določeno v simulacijski datoteki, ki jo operater izbere pred pričetkom simulacije. Simulator je sposoben generirati signale štirih vrst: visok logični nivo, nizek logični nivo, viski pulz, nizek pulz. Razdeljen je na dva dela. Programski del in FPGA del.

• Language: Slovenian
• Keywords: testirana naprava, simulator, simulacijska datoteka, LabVIEW, FPGA, SET signali, CHECK signali, Time Out
• Work type: Bachelor thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2014
• PID: 20.500.12556/RUL-30002
• Publication date in RUL: 06.11.2014

Secondary language

• Language: English
• Title: Testing of the interlock collector device

Abstract

The purpose of simulator which I made is to generate signals for interlock collector device. Interlock collector device is a device which we want to test. A simulator has two versions. First version enables automated simulations and the second version enables manual simulations. Both versions have similar construction and features. The biggest difference is at the front panel. Tested device is connected on simulator through I/O connector of FPGA card and through serial port. Simulator is implemented with National Instruments software called LabVIEW. We must prepare simulation file before start automated simulation. Simulator can generate four different signals: high pulse, low pulse, high level, low level. Simulator is implemented in two parts. Software and hardware.

• Keywords: tested device, simulator, simulation file, LabVIEW, FPGA, SET signals, CHECK signals, Time Out