The open RISC-V instruction set architecture, with its modularity and freely available specification, has become an attractive basis for building custom processing units. The ability to execute instructions, however, does not by itself make a processor useful for solving concrete problems; that requires multitasking and orderly access to input–output devices, which an operating system provides. In this thesis we first identified the hardware mechanisms required by the FreeRTOS real-time operating system — trap handling, control and status registers, and a timer — and then derived the specification of our own core from a comparative analysis of the SweRV EH1, CVA6 and biRISC-V cores. We implemented a 32-bit pipelined processor conforming to the RV32IMC_Zicsr standard, with a six-stage pipeline, a dedicated stage for aligning compressed instructions, an instruction cache, a branch predictor and operand forwarding. The core is described in SystemVerilog and verified through a regression of the riscv-tests suite and co-simulation against the Spike reference model, then integrated over an AXI4 bus into a system on chip on a Nexys A7-100T board. We ported FreeRTOS to the resulting system and built a multi-task demonstration application.
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