20.500.12556/RUL-187856 Načrtovanje in izvedba 32-bitnega procesorja RISC-V s podporo realnočasovnemu operacijskemu sistemu Design and implementation of a 32-bit RISC-V processor with real-time operating system support Odprta ukazna arhitektura RISC-V je zaradi modularnosti in prosto dostopne specifikacije postala privlačna osnova za izdelavo lastnih procesnih enot. Zmožnost izvajanja ukazov pa procesorja še ne naredi uporabnega za reševanje konkretnih problemov; za to sta potrebni večopravilnost in urejen dostop do vhodno-izhodnih naprav, kar zagotovi operacijski sistem. V diplomskem delu smo zato najprej ugotovili, katere strojne mehanizme zahteva realnočasovni operacijski sistem FreeRTOS — obravnavo pasti, kontrolno-statusne registre in časovnik —, nato pa iz primerjalne analize jeder SweRV EH1, CVA6 in biRISC-V izpeljali specifikacijo lastnega jedra. Izdelali smo 32-bitni cevovodni procesor po standardu RV32IMC_Zicsr s šeststopenjskim cevovodom, ločeno stopnjo za poravnavo stisnjenih ukazov, ukaznim predpomnilnikom, napovedovalnikom skokov in posredovanjem operandov. Jedro smo opisali v jeziku SystemVerilog in ga preverili z regresijo nabora riscv-tests ter ko-simulacijo z modelom Spike, nato pa ga prek vodila AXI4 vključili v sistem na čipu na razvojni plošči Nexys A7-100T. Nanj smo prenesli operacijski sistem FreeRTOS in izdelali demonstracijsko aplikacijo z več opravili. The open RISC-V instruction set architecture, with its modularity and freely available specification, has become an attractive basis for building custom processing units. The ability to execute instructions, however, does not by itself make a processor useful for solving concrete problems; that requires multitasking and orderly access to input–output devices, which an operating system provides. In this thesis we first identified the hardware mechanisms required by the FreeRTOS real-time operating system — trap handling, control and status registers, and a timer — and then derived the specification of our own core from a comparative analysis of the SweRV EH1, CVA6 and biRISC-V cores. We implemented a 32-bit pipelined processor conforming to the RV32IMC_Zicsr standard, with a six-stage pipeline, a dedicated stage for aligning compressed instructions, an instruction cache, a branch predictor and operand forwarding. The core is described in SystemVerilog and verified through a regression of the riscv-tests suite and co-simulation against the Spike reference model, then integrated over an AXI4 bus into a system on chip on a Nexys A7-100T board. We ported FreeRTOS to the resulting system and built a multi-task demonstration application. RISC-V RV32IMC FPGA cevovod FreeRTOS SystemVerilog vodilo AXI4 RISC-V RV32IMC FPGA pipeline FreeRTOS SystemVerilog AXI4 bus true false false Slovenski jezik Angleški jezik Diplomsko delo/naloga 2026-09-15 12:05:03 2026-09-15 12:05:12 2026-09-17 03:45:04 0000-00-00 00:00:00 2026 0 0 0000-00-00 NiDoloceno NiDoloceno NiDoloceno 0000-00-00 0000-00-00 0000-00-00 1970-01-01 39031 Jamsek_Urh_-_Nacrtovanje_in_izvedba_32-bitnega_procesorja_RISC-V_s_podporo_realnocasovnemu_opera.pdf Jamsek_Urh_-_Nacrtovanje_in_izvedba_32-bitnega_procesorja_RISC-V_s_podporo_realnocasovnemu_opera.pdf 1 7BBE6DC7D6706423D8E13BC8A01D8213 60bd3b59f9d34e344300f92146432a1223bb1de51673a2e15760899619e6bff2 e981dacc-b0ec-11f1-8bc5-0050569b8976 https://repozitorij.uni-lj.si/Dokument.php?lang=slv&id=247661 Fakulteta za računalništvo in informatiko 0 0 0