This work presents an extension to the Lang24 compiler, enabling the au-
tomatic transformation of loops into vectorized form. This improves the
utilization of parallel processing supported by modern processors. Our focus
is on vector extensions, such as those found in the open RISC-V architec-
ture, which introduces vector registers and instructions. These allow for
clean parallel execution of a single instruction across multiple data points.
The extension is thus capable of pipelined execution at both the instruction
and data levels.
We developed a compiler that allows programmers to activate vector opti-
mization by simply annotating loops, without needing to deal with low-level
programming or using libraries that can complicate software development.
The main challenge lies in data dependencies between operations within the
loop. Data dependencies mean that one iteration of the loop might require
results from the previous iteration, which prevents iterations from being ex-
ecuted in parallel.
The analysis of loops is performed using dependence tests. After this
analysis, the compiler builds a dependency graph, which it uses to generate
vector code optimized for processors with RISC-V architecture and vector
extensions. The final result is assembly code that maximizes execution effi-
ciency and the use of processor resources.
|
