Načrtovanje podvojevalnika napetosti v tehnologiji CMOS

Barachini, Andrej (author), Sešek, Aleksander (mentor)

Generacija napetosti nad napajalno napetostjo je pogosta zahteva pri načrtovanju integriranih vezij, saj je potrebna za pravilno delovanje trajnih pomnilnikov, komunikacije in senzorjev. V tej nalogi obravnavamo načrtovanje kapacitivnega podvojevalnika napetosti oziroma črpalke naboja v tehnologiji CMOS za majhna bremena. V nalogi so predstavljene omejitve tehnologije, osnove kapacitivnih pretvornikov napetosti, ocenjena je primernost obstoječih topologij ter predstavljene predlagane spremembe izbrane topologije za višjo zanesljivost. Ker je v našem primeru izhod črpalke priključen na izhodni priključek čipa, se srečamo tudi z nevarnostjo poškodbe zaradi elektrostatične razelektritve (ESD), zato je bilo potrebno načrtati ustrezno zaščito. Kot zadnje, je k osnovni celici črpalke naboja dodana še regulacija, s katero lahko bolje nadziramo pridobljeno napetost, tudi v primeru variacije bremen in vhodne napetosti - tu so predstavljene različne metode regulacije ter primerjava njihovih prednosti in slabosti. Integrirano vezje črpalke naboja je bilo načrtano v 180 nm tehnologiji CMOS in je uporabljeno za generacijo zaporne napetosti polja fotodiod. Delovanje je bilo preverjeno s simulacijo v programskem paketu Cadence.

• Language: Slovenian
• Keywords: CMOS, črpalka naboja, podvojevalnik napetosti, ESD, integrirano vezje ASIC
• Work type: Master's thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2024
• PID: 20.500.12556/RUL-155390
• COBISS.SI-ID: 190883075
• Publication date in RUL: 29.03.2024

Secondary language

• Language: English
• Title: Voltage doubler design in CMOS technology

Abstract

Generating voltages above the main power supply is often a requirement in the circuit design, as it is needed for correct operation of non-volatile memory, communication or sensors. The thesis addresses the switched-capacitor voltage doubler (single stage charge pump) design for small loads, in CMOS technology. The thesis presents the current technology's limitations, describes basic switched-capacitor voltage converters, evaluates the known topologies and presents upgrades of the chosen topology to improve reliability. Because the charge-pump output is connected to an extrenal pin, it is exposed to electrostatic discharge (ESD) damage, therefore an ESD protection circuit was designed. In conclusion, the regulation of our basic charge pump cell was added for better output voltage control, and additionaly different regulation methods are presented and compared. The charge pump was designed in a 180 nm CMOS technology to generate sufficient photodiode array reverse bias voltage. Correct operation was verified with simulations in Cadence.

• Keywords: CMOS, charge pump, voltage doubler, ESD, ASIC