The thesis describes the process of developing filler cells that are part of a cell library. The cell acts as decoupling capacitor and is used to fill the empty spaces on the chip. The cell provides spare devices for design changes on the chip. It is made in 180 nm technology by the manufacturer TSMC. The components used are NMOS transistors and MIM capacitors. The transistors are connected as capacitors so that the source, drain and substrate are grounded. The gate of the transistor is connected to the supply voltage. First are given the design requirements, which are needed for the cell to work without any errors. The process of selecting components, their connections and their layout is described in detail. The results of the performed simulations are given. The cells will be used in one of the future projects of the company Renishaw d.o o..
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