Razvoj polnilnih celic za integrirana vezja

JANKULOVSKA, VIKTORIJA (author), Trost, Andrej (mentor)

V tem diplomskem delu je opisan postopek razvoja polnilnih celic, ki so del knjižnice celic. Celica deluje kot ločilni kondenzator in se uporablja za zapolnitev prostih mest na čipu. Narejena je v tehnologiji 180 nm proizvajalca TSMC. Uporabljene komponente so NMOS tranzistorji in MIM kondenzatorji. Tranzistorji so povezani kot kondenzatorji tako, da so ponor, substrat in izvor ozemljeni. Vrata tranzistorja so povezana na napajalno napetost. Najprej so podane zahteve, ki jih celica mora izpolniti za brezhibno delovanje. Podrobno je opisan postopek izbire komponent in njihove povezave ter njihova postavitev. Podani so rezultati izvedenih simulacij. V podjetju Renishaw d.o.o. bo ta celica uporabljena v enem izmed prihodnjih projektov.

• Language: Slovenian
• Keywords: celica, ločilni kondenzator, zapolnitev mest, ASIC, Cadence Virtuoso
• Work type: Bachelor thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2022
• PID: 20.500.12556/RUL-139376
• COBISS.SI-ID: 120038659
• Publication date in RUL: 01.09.2022

Secondary language

• Language: English
• Title: Development of filler cells for integrated circuits

Abstract

The thesis describes the process of developing filler cells that are part of a cell library. The cell acts as decoupling capacitor and is used to fill the empty spaces on the chip. The cell provides spare devices for design changes on the chip. It is made in 180 nm technology by the manufacturer TSMC. The components used are NMOS transistors and MIM capacitors. The transistors are connected as capacitors so that the source, drain and substrate are grounded. The gate of the transistor is connected to the supply voltage. First are given the design requirements, which are needed for the cell to work without any errors. The process of selecting components, their connections and their layout is described in detail. The results of the performed simulations are given. The cells will be used in one of the future projects of the company Renishaw d.o o..

• Keywords: cell, decoupling capacitor, filling spaces, ASIC, Cadence Virtuoso