Načrtovanje močnostnega trans-konduktančnega ojačevalnika razreda AB v tehnologiji CMOS za velika kapacitivna bremena

BRUS, DARJAN (author), Strle, Drago (mentor)

Potreba po transkonduktančnih ojačevalnikih, ki krmilijo velika kapacitivna bremena, je razširjena v veliko aplikacijah. Magistrska naloga obravnava načrtovanje močnostnega transkonduktančnega ojačevalnika razreda AB v tehnologiji CMOS za velika kapacitivna bremena. V tej magistrski nalogi so ovrednoteni obstoječi načini krmiljenja in kompenzacije ojačevalnikov, ki poganjajo velika kapacitivna bremena, kot so Millerjeva kompenzacija, CBMC, DACFC, STCB in kompenzacija s prilagodljivim nelinearnim bremenom. Glede na lastnosti ojačevalnikov iz literature je bila izbrana topologija ojačevalnika opisanega v tej nalogi, ki je kombinacija ojačevalnika s prepognjeno kaskodo za prvo ojačevalno stopnjo in kombinacija STCB bloka za doseganje velikih tokov in Millerjevo kompenzacijo za drugo močnostno ojačevalno stopnjo. Za izbrano topologijo je bil najprej opravljen teoretičen izračun stabilnosti, s katerim smo predvideli, kakšna ojačenja in kompenzacijske kondenzatorje potrebujemo za doseganje želenih tokovnih zmogljivosti in pasovne širine ojačevalnika. Po teoretični potrditvi sledi analiza vezja preko simulacij v računalniškem orodju za načrtovanje analognih vezij, kjer je podrobno analizirano celotno vezje pri vseh robnih pogojih, ki jih postavljajo temperatura, napajalna napetost in procesni parametri izdelave tranzistorjev. S simulacijami smo potrdili, da je ta topologija ojačevalnika primerna za krmiljenje 110 Ω bremena vzporedno s kondenzatorjem do velikosti 1 nF in da dosega ojačenje enako ena do približno 700 kHz pasovne širine. Po potrditvi delovanja ojačevalnika s simulacijami smo pripravili maske za izdelavo ojačevalnika v TSMC 180 nm BCD tehnologiji. Delovanje ojačevalnika je na koncu potrjeno z meritvami opravljenimi pri sobni temperaturi, ki so pokazale, da se delovanje ojačevalnika pri večini meritev ujema z rezultati simulacij, saj so bile izmerjene vrednosti pri večini meritev znotraj vrednosti dobljenih v simulacijah.

• Language: Slovenian
• Keywords: močnostni ojačevalnik, razred AB, transkonduktančni, velika kapacitivna bremena, integrirano vezje ASIC, CMOS
• Work type: Master's thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2021
• PID: 20.500.12556/RUL-124763
• Publication date in RUL: 15.02.2021

Secondary language

• Language: English
• Title: Design of class AB transconductance power amplifier in CMOS technology for large capacitive loads

Abstract

The need for transconductance amplifiers that control high capacitive loads is widespread in many applications. The master’s thesis deals with the design of class AB transconductance power amplifier in CMOS technology for large capacitive loads. In this master’s thesis, the existing methods of control and compensation of amplifiers that drive large capacitive loads, such as Miller compensation, CBMC, DACFC, STCB, compensation with adaptive nonlinear load, are evaluated. Based on the properties of the amplifiers from the literature, the amplifier topology described in this paper was chosen, which is a combination of an folded cascade amplifier for the first amplifier stage and a combination of STCB block to achieve high currents and Miller compensation for the second power amplifier stage. For the selected topology, a theoretical stability calculation was first performed to predict what kind of amplification and compensation capacitors are needed to achieve the desired amplifier output current and bandwidth. Theoretical confirmation is followed by circuit analysis via simulations in a computer tool for analog circuit design, where the entire circuit is analyzed in detail at all boundary conditions set by temperature, voltage supply, and process parameters of transistors. The simulations confirmed that this amplifier topology is suitable for controlling a 110 Ω load in parallel with a capacitor up to 1 nF and that the unity gain reaches to about 700 kHz bandwidth. After the simulations confirmed the operation of the amplifier, we prepared masks for the manufacture of the amplifier in TSMC 180 nm BCD technology. The performance of the amplifier was finally confirmed by measurements performed at room temperature, which showed that the performance of the amplifier in most measurements matched the results of the simulations, as the measured values in most measurements were within the values obtained in the simulations.

• Keywords: power amplifier, class AB, transconductance, high capacitive loads, integrated circuit ASIC, CMOS