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Časovno digitalni pretvornik visoke ločljivosti na čipu Xilinx Zynq-7010
Adamič, Michel (Author), Pestotnik, Rok (Mentor) More about this mentor... This link opens in a new window, Trost, Andrej (Co-mentor)

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Abstract
V sklopu tega magistrskega dela smo se lotili izdelave hitrega časovno-digitalnega pretvornika visoke ločljivosti na cenovno dostopni plošči Red Pitaya, ki temelji na zmogljivem polno programirljivem čipu Xilinx Zynq 7010. Časovno-digitalni pretvornik (TDC) je popolnoma digitalen in v celoti implementiran na programirljivem polju vrat (FPGA) v ravnokar omenjenem čipu, tako da za opravljanje meritev ne potrebujemo nobenih dodatnih zunanjih komponent. TDC je bil zasnovan po principu časovne interpolacije, kjer čas štejemo z uporabo sinhronega binarnega števca, za zelo natančno določitev časa prihoda med urinimi cikli pa skrbi integrirana zakasnilna linija. Posamezen kanal TDC je na voljo v obliki strojne komponente intelektualne lastnine (jedra IP) z vmesnikom AXI, kar je zelo priročno za gradnjo večkanalnih sistemov. Procesni sistem Zynq bere časovne značke aktivnih časovno-digitalnih pretvornikov in jih preko omrežja Ethernet pošilja odjemalcu, recimo osebnemu računalniku, kjer jih lahko ustrezno obdelamo in prikažemo v grafičnem uporabniškem vmesniku. V sklopu tega magisterija smo implementirali dva kanala TDC in ju podrobno okarakterizirali. Posamezen časovno-digitalni pretvornik teče na frekvenci 350~MHz in je ob mrtvem času $\sim$14~ns sposoben vzorčiti do 70 milijonov značk na sekundo. Časovna ločljivost posameznega kanala dosega odličnih 11~ps in ostane zelo visoka tudi pri večjih časovnih intervalih, vsaj nekje do 100~ns. Izkazalo se je, da lahko tudi s povsem običajnimi signali s hitrostjo naraščanja 10~ns opravljamo meritve visoke ločljivosti, prav tako pa je meritev robustna na spremembe temperature. Izdelani TDC je zelo natančen in periodo zunanjega signala izmeri z relativno natančnostjo $10^{-5}$ v 60 stopinj širokem temperaturnem intervalu. Nazadnje smo inštrument preizkusili še v realistični postavitvi s pulznim laserjem in hitro silicijevo fotopomnoževalko (SiPM), kjer se je novi TDC odlično obnesel. Vse to dokazuje, da se da z izbiro primerne arhitekture in modernega čipa FPGA tudi na cenovno zelo dostopnih platformah, kot je Red Pitaya, implementirati izredno zmogljiv časovni merilni inštrument, ki je uporaben tako za študente kot profesionalne raziskovalce.

Language:Slovenian
Keywords:časovno-digitalni pretvornik, TDC, hitra digitalna vezja, FPGA, Zynq, zakasnilna linija, prenosna logika, pikosekundna ločljivost
Work type:Master's thesis/paper (mb22)
Tipology:2.09 - Master's Thesis
Organization:FMF - Faculty of Mathematics and Physics
Year:2020
COBISS.SI-ID:23969539 This link opens in a new window
Views:640
Downloads:316
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Secondary language

Language:English
Title:A High-Resolution Time-to-Digital Converter in a Xilinx Zynq-7010 SoC
Abstract:
This Master’s Thesis presents an implementation of a fast high-resolution time-to-digital converter (TDC) on the affordable Red Pitaya board, featuring a powerful all programmable Xilinx Zynq 7010 SoC. The design is fully digital, enabling the TDC to be implemented entirely within the Zynq FPGA, thus requiring no additional external components. The architecture of the TDC is based on the time interpolation technique which employs a coarse binary counter and a tapped delay line for fine time measurements between adjacent clock cycles. A TDC channel is packaged into an AXI-interfaced IP core, making it easy to build multichannel systems. Produced timestamps from active TDC channels are read by the Zynq processing system and sent via Ethernet to a client, for example a PC which can process and display them with a graphical user interface. A two-channel TDC system has been implemented and thoroughly characterized during this Thesis work. An individual channel runs at 350~MHz and has a dead time of $\sim$14~ns, sampling up to 70 million timestamps per second. Its time resolution can reach an astounding 11~ps and remains very high even at larger time intervals of up to 100~ns. It turned out that high-resolution measurements can also be done with standard 10~ns rise time signals and with widely varying temperatures. The implemented TDC is very accurate and can measure the period of an externally applied signal with relative accuracy of $10^{-5}$ over a 60 degree temperature swing. Finally, the instrument was put to the test in a realistic setup with a pulsed laser and a fast silicon photomultiplier (SiPM), where the new TDC performed exceedingly well. This concludes that by choosing the right architecture and a modern FPGA, a very powerful time measurement instrument, useful both for students and professionals, can be implemented on perfectly affordable hardware platforms such as the Red Pitaya.

Keywords:time-to-digital converter, TDC, high-speed digital circuit design, FPGA, Zynq, tapped delay line, carry chain, picosecond resolution

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