This Master’s Thesis presents an implementation of a fast high-resolution time-to-digital converter (TDC) on the affordable Red Pitaya board, featuring a powerful all programmable Xilinx Zynq 7010 SoC. The design is fully digital, enabling the TDC to be implemented entirely within the Zynq FPGA, thus requiring no additional external components. The architecture of the TDC is based on the time interpolation technique which employs a coarse binary counter and a tapped delay line for fine time measurements between adjacent clock cycles. A TDC channel is packaged into an AXI-interfaced IP core, making it easy to build multichannel systems. Produced timestamps from active TDC channels are read by the Zynq processing system and sent via Ethernet to a client, for example a PC which can process and display them with a graphical user interface. A two-channel TDC system has been implemented and thoroughly characterized during this Thesis work. An individual channel runs at 350~MHz and has a dead time of $\sim$14~ns, sampling up to 70 million timestamps per second. Its time resolution can reach an astounding 11~ps and remains very high even at larger time intervals of up to 100~ns. It turned out that high-resolution measurements can also be done with standard 10~ns rise time signals and with widely varying temperatures. The implemented TDC is very accurate and can measure the period of an externally applied signal with relative accuracy of $10^{-5}$ over a 60 degree temperature swing. Finally, the instrument was put to the test in a realistic setup with a pulsed laser and a fast silicon photomultiplier (SiPM), where the new TDC performed exceedingly well. This concludes that by choosing the right architecture and a modern FPGA, a very powerful time measurement instrument, useful both for students and professionals, can be implemented on perfectly affordable hardware platforms such as the Red Pitaya.
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