The goal of master thesis was to develop a framework for the development and acceleration of fully connected neural networks in FPGAs. We implement fully connected neural networks using Intel® FPGA SDK for OpenCL. To fully exploit the efficiency of FPGA’s fixed-point arithmetic operations on one hand and adaptiveness of neural networks on the other hand, we use fixed-point number representation and approximate multipliers.
We perform experiments with iterative logarithmic multiplier (ILM) and a hybrid logarithmic-booth encoding multiplier (LOBO). Using simple iterative learning methods with approximate multipliers we could not successfully train neural networks. Configuration of a neural network using ILM with one correction circuits shows the best results during inference. In most cases, using the approximate multipliers, the compiler synthesises circuits with higher clock frequency and more balanced usage of FPGA's resources.
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