Programiranje adaptivnih algoritmov na vezjih FPGA z ogrodjem OpenCL

Palčič, Žan (author), Lotrič, Uroš (mentor), Bulić, Patricio (comentor)

V magistrskem delu smo razvili programsko ogrodje za realizacijo in pohitritev delovanja polno povezanih nevronskih mrež na vezjih FPGA. Nevronske mreže so izvedene v visoko-nivojskem ogrodju OpenCL z nekaj prilagoditvami za vezja FPGA. Zaradi učinkovitosti vezja FPGA pri računanju s števili v fiksni vejici in zaradi prilagodljivih polno povezanih nevronskih mrež, smo uporabili približne množilnike in števila v fiksni vejici. Uporabili smo iterativni logaritmični množilnik ILM in hibridni logaritmični množilnik LOBO. Z enostavnim iterativnim učenjem in z uporabo približnih množilnikov nismo uspeli naučiti nevronske mreže. Pri napovedovanju se je najbolje izkazala nevronska mreža s približnim množilnikom ILM z enim korekcijskim vezjem. S približnimi množilniki smo v večini primerov uspeli sintetizirati vezja z višjo frekvenco ure in hkrati dosegli bolj uravnoteženo porabo različnih gradnikov na vezju FPGA.

• Language: Slovenian
• Keywords: FPGA, OpenCL, adaptivni algoritmi, umetna nevronska mreža, približni množilniki
• Work type: Master's thesis/paper
• Organization: FRI - Faculty of Computer and Information Science
• Year: 2019
• PID: 20.500.12556/RUL-113279
• COBISS.SI-ID: 1538500547
• Publication date in RUL: 18.12.2019

PALČIČ, Žan, 2019, Programiranje adaptivnih algoritmov na vezjih FPGA z ogrodjem OpenCL [online]. Master’s thesis. [Accessed 24 April 2025]. Retrieved from: https://repozitorij.uni-lj.si/IzpisGradiva.php?lang=eng&id=113279

Secondary language

• Language: English
• Title: Programming adaptive algorithms on FPGA with OpenCL

Abstract

The goal of master thesis was to develop a framework for the development and acceleration of fully connected neural networks in FPGAs. We implement fully connected neural networks using Intel® FPGA SDK for OpenCL. To fully exploit the efficiency of FPGA’s fixed-point arithmetic operations on one hand and adaptiveness of neural networks on the other hand, we use fixed-point number representation and approximate multipliers. We perform experiments with iterative logarithmic multiplier (ILM) and a hybrid logarithmic-booth encoding multiplier (LOBO). Using simple iterative learning methods with approximate multipliers we could not successfully train neural networks. Configuration of a neural network using ILM with one correction circuits shows the best results during inference. In most cases, using the approximate multipliers, the compiler synthesises circuits with higher clock frequency and more balanced usage of FPGA's resources.

• Keywords: FPGA, OpenCL, Adaptive algorithms, Artificial neural network, Approximate multipliers