Graphs are frequently used in cases where data to be described is densely interconnected or the information about said connections, also referred to as topology of the data, is more important than the data itself. Common solutions to graph processing and computation often rely on software, which in itself is a burden to the conventional widespread computer architecture. Henceforth, the need for an efficient hardware implementation of graph structures and their manipulation arises. This work is a treatise on hardware accelerated graph computation. It provides some knowledge about graphs and graph algebra, for use in what endeavours in the matter follow. It conveys some information on graph data structure and graph database. The latter is followed by the conception of the graph processor architecture and the reasoning behind it. Lastly, some details of a suitable implementation using an FPGA circuit are given and some common protocols are described to achieve a good overall integration as well as the integration of the processor itself.
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