Vrednotenje faznega šuma v ulomkovi fazno sklenjeni zanki

Blatnik, Aljaž (author), Vidmar, Matjaž (mentor)

Delo se ukvarja z vrednotenjem faznega šuma ulomkove fazno sklenjene zanke. Z opisom teoretičnega ozadja delovanja PLL zanke tako v celoštevilskem kot ulomkovem načinu preide v opis posameznih gradnikov skupaj s tehnološkimi omejitvami in primeri izvedbe. Fazni šum je opisan iz primera vrste šuma, tako matematično kot vizualno, v primeru vklenjene zanke. Praktični del predstavlja gradnjo frekvenčnega izvora s pomočjo integriranega čipa MAX2871, dodana so tudi navodila, kako prototip sestavimo v domači delavnici s pomočjo široko dostopnih orodji. Predstavljeni so podporni sistemi za komunikacijo s PLL čipom preko USB povezave, ter metoda za samodejno merjenje faznega šuma s pomočjo programskega jezika Python, ter spektralnega analizatorja. Meritve prikazujejo vpliv različnih načinov delovanja na spreminjanje faznega šuma. Izmerjen je vpliv toka črpalke naboja, stopnja linearnosti, ter različni režimi za izločanje neželenih špičk. Predstavljena je tudi samodejna meritev faznega šuma v celotnem frekvenčnem področju. V zaključnem delu je predstavljena izvedba fazno sklenjene zanke s FPGA, ki je bila sicer uspešna, a s stališča faznega šuma zaradi presluha v notranjosti čipa slaba.

• Language: Slovenian
• Keywords: fazni šum, fazno sklenjena zanka, ulomkovni način delovanja, programabilni čip, MAX2871, Python, ARM Cortex-M0
• Work type: Master's thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2017
• PID: 20.500.12556/RUL-91113
• Publication date in RUL: 20.03.2017

BLATNIK, Aljaž, 2017, Vrednotenje faznega šuma v ulomkovi fazno sklenjeni zanki [online]. Master’s thesis. [Accessed 8 June 2025]. Retrieved from: https://repozitorij.uni-lj.si/IzpisGradiva.php?lang=eng&id=91113

Secondary language

• Language: English
• Title: Evaluating the phase noise of a fractional phase-locked loop

Abstract

The work deals with the evaluation of the phase noise in the fractional phase locked loop. The theoretical background of the PLL loop in both integer and fractional mode is presented. Description of each component along with the techical limitations and examples is added. Phase noise is described both mathematically and visually in the case of the locked loop system. The practical part presents the construction of the frequency source by means of the integrated chip MAX2871. Instructions on how to assemble a prototype in the home workshop by using widely available tools are also added. Support systems to communicate with PLL chip via a USB connection, and a method for automatically measuring the phase noise by using the programming language Python and the spectrum analyzer are described at the end of the chapter. Phase noise measurements of MAX2871 were performed at different modes in acton, changes in the charge pump current, degree of linearity and modes for reducing unwanted spurs. Automatic method of complete spectrum measurment is also presented. In the final part, implementation of phase locked loop with FPGA is described, which although has been successful, was from the standpoint of phase noise bad due to crosstalk inside the chip.

• Keywords: phase noise, phase locked loop, fractional mode, field programmable gate array, MAX2871, Python, ARM Cortex-M0