The PhD thesis deals with the implementation of a color sensor and an analog to digital con-
verter on a single chip. The thesis presents the implementation of sigma delta modulator and the color sensor without additional optical filters, or additional expensive technology steps to achieve color selectivity and high resolution. The integrated circuit (System on Chip – SoC), which includes three photo-diodes and the modulator is implemented in a standard 130 nm twin-well CMOS process, with 6 metal layers. The color sensor is a combination of three photodiodes with different spectral responses for different wavelengths of visible light. Ideally the produced color sensor responsivity should match to RGB color-match function. To achieve matching, a set of transformation matrices is used to match the produced response to the RGB color space for different light sources. Appropriate statistical training assures minimum error for the color placement in the color space for different light sources. Three different photodiodes are used; one with a “green”, the second with “blue” and the third with “red” response. Because light has different penetration depth at different wavelengths, different layers can be used. For a ‘‘red’’ response, the N-well and P-substrate is used; for a ‘‘green’’ response, the N+ and P-substrate is used and for a ‘‘blue’’ response a N+ and P-
well is used. The light generated current of the photodiodes is in the range from 0.1 pA to 300 nA, which translates to a dynamic range of 120 dB. To achieve resolution of 0.1 pA and a dynamic range bigger that 120 dB, a sigma-delta modulator architecture was selected. High dynamic range, high linearity and 20 – bit resolution is achieved with third order sigma delta modulator with a one-bit internal quantizer, which of-
fers a theoretical signal to quantization noise ratio of 148 dB. Additional advantage of the ΣΔ modulator is its ability to convert input current directly into a digital “bit-stream”. This is possible due to the fact, that the first integrating stage is continuous time and converts the photo-current of the light directly into voltage, while the second and the third integrator remain discrete time, and offer more accurate placement of poles and zeros of the noise transfer function. Continuous time integrator in the first stage simplifies the requirements of the operational amplifier like: bandwidth, slew rate, power consumption and offers lower noise. Unfortunately the continuous time integrating stage is susceptible to clock jitter and to process and environmental parameters. To reduce the clock jitter influence on the signal to noise ratio an additional FIR-DAC filter is placed in the feedback loop. The filter acts as a multi – bit digital to analog converter with inherent linearity of a single – bit digital to analog converter. The added FIR-DAC filter reduces the amplitudes of the output steps of the digital to analog converter and thus reduces the effect of the clock jitter. This work presents the model and the system level simulations of the modulator, the circuit implementation and the spice simulation results, which are compared to system level simulation results for confirmation. The modulator and the photodiodes are implemented in twin-well 130nm CMOS process with 6 metal layers. Measured results confirm the functionality of the circuit and achieved dynamic range and linearity
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