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Optimizacija referenčnega vezja na osnovi energijske reže v tehnologiji CMOS
BERČAN, DAMJAN (Author), Trontelj, Janez (Mentor) More about this mentor... This link opens in a new window

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Abstract
Magistrsko delo predstavlja načrtovanje in optimizacijo napetostnega referenčnega vira na osnovi energijske reže v CMOS tehnologiji. Iz simulacij v 0,18 μm in 0,35 μm tehnologiji smo ugotovili, da z uporabo kompenzacije drugega reda dobimo boljši temperaturni koeficient (TK) referenčne napetosti. Referenčna napetost je sestavljena iz napetosti z negativnim temperaturnim koeficientom in pozitivnim temperaturnim koeficientom ter kompenzacijske napetosti. V 0,18 μm tehnologiji referenčna napetost znaša 1,348 V. Simulacije smo izvedli v temperaturnem območju od -40 ◦C do 125 ◦C. TK znaša 9,48 ppm/◦C in rejekcijski faktor napajalne napetosti (PSRR) je -65 dB pri nizkih frekvencah. Vpliv spremembe napajalne napetosti na referenčno napetost znaša 0,25 μV/mV v napetostnem območju od 3 V do 3,6 V. Cilj optimizacije v 0,35 μm tehnologiji je bil dobiti TK boljši od 20 ppm/◦C v temperaturnem območju od -40 ◦C do 150 ◦C. TK je blizu 13 ppm/◦C in PSRR -68,1 dB pri nizkih frekvencah. Vpliv spremembe napajalne napetosti na referenčno napetost znaša 0,40 μV/mV v napetostnem območju od 3 V do 3,6 V. Aktivna površina integriranega vezja znaša 0,073 mm2. Simulacijski rezultati z modeli dveh različnih proizvajalcev v 0,35 μm tehnologiji so pokazali veliko razliko v temperaturnem koeficientu referenčne napetosti. Rezultati meritev izdelanega vezja v 0,35 μm CMOS tehnologiji so pokazali, da se TK in vpliv spremembe napajalne napetosti na referenčno napetost dobro ujemata s simulacijskimi rezultati.

Language:Slovenian
Keywords:Referenčno vezje na osnovi energijske reže, kompenzacija drugega reda, optimizacija referenčnega vezja
Work type:Master's thesis/paper (mb22)
Organization:FE - Faculty of Electrical Engineering
Year:2016
Views:747
Downloads:388
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Secondary language

Language:English
Title:CMOS Band-gap reference circuit optimization
Abstract:
The thesis addresses the design optimization of bandgap voltage reference in CMOS technology. The conclusion obtained from computer simulations in 0.18μm and 0.35μm technology is that the second order compensation circuit can improve temperature coefficient (TC) of reference voltage. The bandgap voltage is a sum of a negative TC voltage, a positive TC voltage and a compensation voltage. Simulations based on 0.18μm CMOS technology provide a reference voltage of 1.348V. The TC is 9.48ppm/◦C in temperature range between -40◦C to 125◦C. The power supply rejection ratio (PSRR) is -65dB at low frequencies. The line regulation of voltage reference is 0.25μV/mV with supply voltage variation from 3V to 3.6V. The target of optimization in the 0.35μm techonology was to achieve better than 20ppm/◦C in temperature range between -40 to 150◦C. The resulting temperature coefficient in simulations is close to 13ppm/◦C. The PSRR is -68.1dB at low frequencies. The line regulation of voltage reference is 0.40μV/mV with supply voltage variation from 3V to 3.6 V. The bandgap reference occupies 0.073mm2. A comparison of simulated results between models of two different foundries in 0.35μm technology shows significant differences in reference voltage temperature coefficient. Measurement results of the fabricated integrated ciruit show good complience of the reference voltage TC and line regulation with the simulation results.

Keywords:Bandgap voltage reference, second order compensation, optimization of reference circuit

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