Grafični krmilnik VGA v sistemu na integriranem vezju

ROME, VITO (author), Trost, Andrej (mentor)

V diplomskem delu sem načrtoval in realiziral grafično enoto, ki je s pomočjo zunanjega krmiljenja sposobna prikazovati VGA signal različnih ločljivosti. Prikazan in realiziran je koncept hitrega prenosa in sprejema slikovnega zapisa BMP prek mrežnega Ethernet vmesnika in njegov prikaz v realnem času na VGA monitorju. Ogrodje sistema je preprosto in omogoča nadaljne razširitve tako v strojni kot programski implementaciji. Integrirano razvojno vezje ZedBoard s SoC čipom Zynq-7020, proizvajalca Xilinx, predstavlja osrednji gradnik FPGA sistema. Integrirano vezje poleg programirljive logike (PL), ki sloni na Artix-7 družini vezja FPGA, vsebuje tudi procesorski del (PS), ki ga poganja dvojedrni ARM Cortex-A9 procesor. Vezje nudi realizacijo hibridnih rešitev in nam omogoča izvedbo časovno kritičnih funkcij, ki jih implementiramo v PL delu, medtem ko PS del skrbi za sistemsko delovanje. V PL delu vezja realiziramo celoten strojni del grafične enote, od generatorja ure različnih period potrebnih pri spreminjanju ločljivosti VGA signala, komponente z generatorjem sinhronizacijskih signalov, do prikaza slike iz BRAM pomnilnika, delne obdelave slike in pravilnega končnega prikaza na VGA izhodu razvojne plošče. PS del vezja poganja programsko kodo, ki skrbi za konfiguracijo ter vmesno spreminjanje registrov perifernih komponent vezja. Prav tako PS del vezja izvaja operacijski sistem FreeRTOS, ki med drugim omogoča UDP protokol Ethernet komunikacije. S tem poskrbimo za prenos slike s TFTP odjemalcem in prepis v BRAM pomnilnik. S spreminjanjem registrov vplivamo na delovanje perifernih komponent in posledično na prikaz končnega VGA signala željene ločljivosti.

• Language: Slovenian
• Keywords: BMP, VGA, SoC, FPGA, Xilinx, Zynq, FreeRTOS, Ethernet, TFTP, BRAM, grafična enota, ločljivost zaslona
• Work type: Undergraduate thesis
• Organization: FE - Faculty of Electrical Engineering
• Year: 2016
• PID: 20.500.12556/RUL-84126
• Publication date in RUL: 11.07.2016

Secondary language

• Language: English
• Title: VGA graphics controller in system-on-chip

Abstract

The thesis describes development of graphic unit capable of setting different VGA screen resoultions selected by user. The concept of receiving BMP file format through Ethernet controller is performed and shown on VGA monitor in real time. The sistem's framework is kept simple and allows further updates in both hardware and software implementation. The Zedboard development kit with Zynq-7020 SoC integrated circuit, manufactured by Xilinx, is the sistem's main block. On the same die there are programmable logic (PL) of integrated circuit that belongs to the Artix-7 FPGA devices family and processing system (PS) containing two ARM based Cortex-A9 processors. The hybrid solutions where timing-critical functions are required can be performed with the use of PL while the PS takes care of other system tasks. The complete hardware logic of graphic unit resides in PL circuit. It consist of pixel clock generator needed to other blocks when adjusting screen resolutions, block that generates synhronization pulses, block that reads out data from BRAM, block for processing image and block of delivering final image to the VGA output of the circuit. The PS part of the circuit runs program code that firstly intializes PL peripheral components and secondly reads of writes into registers and therefore affects the behaviour of PL peripheral components during execution of the program. The PS also runs real time operating system FreeRTOS which delivers the use of TCP/IP stack and UDP protocol. With a simple TFTP client the BMP file can be transferred into the circuit and it's internal component BRAM. Affecting the behaviour of PL peripheral components delivers the selected screen resoultion to the VGA output.

• Keywords: BMP, VGA, SoC, FPGA, Xilinx, Zynq, FreeRTOS, Ethernet, TFTP, BRAM, graphic unit, screen resolution