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Zasnova in izvedba računskega jedra OpenCL z vezjem FPGA
MARAŽ, DOMEN (Author), Žemva, Andrej (Mentor) More about this mentor... This link opens in a new window

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Abstract
V diplomskem delu smo predstavili zasnovo in izvedbo računskega jedra OpenCL z vezjem FPGA. Uvodoma smo podali problematiko in ključne rešitve za povečevanje zmogljivosti in učinkovitosti procesnih sistemov. Predstavili smo heterogene sisteme, navedli njihov razvoj in izvedbe strojne opreme. Načrtovanje programske opreme za tovrstne sisteme je izredno kompleksno. Rešitev je v ogrodju OpenCL, ki ga je zasnovalo podjetje Apple Inc. in ga prepustilo krovni organizaciji Khronos Group. V delu je predstavljen osnovni koncept ogrodja OpenCL in komponente, ki sestavljajo program napisan za heterogene sisteme. Namen ogrodja OpenCL je splošna uporabnost programa na različni strojni opremi. Za ta namen je podjetje Altera razvilo razvojno okolje Altera SDK za OpenCL, ki smo ga v delu detajlno predstavili. Osredotočili smo se na izvedbo računskega jedra z vezjem FPGA, saj ta predstavlja pomemben del razvoja heterogenih sistemov. Vezja FPGA se vse več pojavljajo v visoko zmogljivih računalniških sistemih HPC in v vgrajenih sistemih, kjer je pomemben dejavnik učinkovitost procesiranja. V primerjalni študiji smo primerjali čas izvajanja funkcije matričnega množenja na računskem jedru OpenCL z vezjem FPGA in z izvajanjem funkcije na splošnem procesorju CPU. Primerjali smo tudi različne izvedbe računskega jedra. Ugotovili smo: (i) da je čas izvajanja funkcije na računskem jedru OpenCL hitrejše za faktor 131 in (ii) da je računsko jedro FPGA-B za faktor 15 hitreje izvršilo funkcijo v primerjavi z FPGA-A.

Language:Slovenian
Keywords:OpenCL, FPGA, heterogeni sistemi, računsko jedro, Altera
Work type:Undergraduate thesis (m5)
Organization:FE - Faculty of Electrical Engineering
Year:2016
Views:876
Downloads:334
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Secondary language

Language:English
Title:Design and implementation of OpenCL kernel in FPGA device
Abstract:
In this thesis we introduce a design and implementation of OpenCL kernel in FPGA. Initially we presented limits of increasing performances of traditional CPU technology. The end of frequency scaling has caused a shift to multicore processing. However, multicore processing has diminishing returns in terms of increasing true application performance due to limits in I/O and memory bandwidth. Heterogeneous computing is a solution to increase performances and efficiencies. However, writing software application for such computing system is a quite challenging. OpenCL is a framework for heterogeneous systems, which was developed by Apple Inc., but is now maintained by the Khronos Group. It allows programs to run on multicore CPUs, GPUs, DSPs and FPGAs. Altera introduced the SDK for OpenCL which convert the OpenCL code to kernels that can be run on an FPGA device. In this thesis we present a user-centric overview of Altera SDK for OpenCL. In the comparison study we take matrix multiplication function and compare the ordinary CPU execution time and the computed kernel time on FPGA. Within the same comparison study we compare computed kernel time of optimized FPGA-B kernel and non-optimized FPGA-A kernel as well. We find out, (i) that same calculation using the OpenCL model provide a speed of 131 times over the ordinary CPU execution and (ii) that only kernel optimization provide a speed of 15 times.

Keywords:OpenCL, FPGA, heterogeneous computing, kernel, Altera

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