Zasnova in izdelava testne naprave Ethernet v vezju SoC FPGA

CIGLIČ, JURE (author), Žemva, Andrej (mentor)

Pri razvoju sodobnih, več gigabitnih omrežnih naprav se pogosto srečamo z izzivom njihovega testiranja in karakterizacije. V sklopu diplomskega dela je predstavljen razvoj omrežne testne naprave od začetnih tehnoloških zahtev, izbire ključnih komponent, pa vse do končne implementacije in testiranja. Integrirano vezje Arria V ST SoC FPGA, proizvajalca Altera, predstavlja osrednji gradnik sistema. Samo integrirano vezje spada v družino sistemov na čipu, ki poleg programabilne logike (FPGA) vsebuje tudi procesorski del (ang. hard processor system HPS), zasnovan okoli dvojedrnega procesorja ARM Cortex-A9. Vezje omogoča razvoj hibridnih rešitev, kjer časovno kritične funkcije implementiramo v programabilni logiki, procesorski del pa skrbi za sistemsko delovanje. V našem primeru so v programabilnem delu vezja implementirani 10 Gbps Ethernet vmesnik, logika za sestavljanje in preverjanje paketov ter vmesnik za posredovanje paketov procesorskemu delu. Procesorski del izvaja programsko kodo, ki skrbi za konfiguracijo perifernih naprav, programabilne logike in zagon operacijskega sistema Linux. Le-ta nam preko Ethernet vmesnika, implementiranega v programabilnem delu vezja, omogoča povezljivost naprave v omrežje in izvajanje programa za konfiguracijo ter kontrolo paketnega generatorja. Kontrolni program omogoča izvajanje dveh testov. Prvi test izvaja meritev propustnosti in zakasnitve testiranega sistema. Drugi test je namenjen testiranju stabilnosti testiranega sistema. Praktični prikaz delovanja testne naprave je izveden na testni plošči Arria V SoC FPGA Development Board, proizvajalca Altera.

• Language: Slovenian
• Keywords: omrežna testna naprava, Altera, Arria V ST SoC FPGA, FPGA, HPS, 10 Gbps Ethernet vmesnik, test stabilnosti, meritev propustnosti, meritev zakasnitve
• Work type: Undergraduate thesis
• Organization: FE - Faculty of Electrical Engineering
• Year: 2016
• PID: 20.500.12556/RUL-81754
• Publication date in RUL: 09.05.2016

Secondary language

• Language: English
• Title: Design and implementation of Ethernet testing device in SoC FPGA circuit

Abstract

The development of multi-gigabit network devices often brings about challenges concerning their validation and characterization. The present thesis describes the development of a network test device from initial device requirements, the selection of the main building blocks to the final implementation and testing. The Altera Arria V SoC FPGA integrated circuit, manufactured by Altera, is the system's main building block. It belongs to the family of the so-called System on a Chip (SoC) integrated circuits which integrate FPGA fabric and an ARM-based hard processor system (HPS) on the same die. Integrated circuit allow us to develop the so-called hybrid solutions where timing-critical functions are implemented in the FPGA fabric and processor take care of system operation. In our case, the 10 Gbps Ethernet controller, the logic for assembling and verifying test packets and the interface for forwarding packets to the processor are implemented in the FPGA portion of the integrated circuit. The HPS part uses the Linux operating system for controlling peripheral devices and execution of control software that configures and controls the packet generator. The Ethernet controller implemented in the FPGA part of the integrated circuit enables the processor to connect to the network. The control software allows us to execute two types of tests. The first test measures tested system bandwidth and latency. The second test verifies tested system stability. The Altera Arria V Soc FPGA Development Board was used for demonstration.

• Keywords: network test equipment, Altera, Arria V ST SoC FPGA, FPGA, HPS, 10 Gbps Ethernet, stability test, bandwidth and latency measurement