Hardware implementation of Falcon post-quantum signature scheme

Smole, Vid (author), Pilipović, Ratko (mentor), Sinha Roy, Sujoy (comentor), Aikata, Aikata (comentor)

Quantum computers threaten to break current signature algorithms, prompting NIST to standardize multiple post-quantum signature algorithms, including Falcon. Falcon's reliance on floating-point arithmetic and recursive algorithms makes designing efficient hardware implementations difficult. This thesis presents the first unified accelerator for signature generation and signature verification for Falcon-512 and Falcon-1024 completely in hardware. Synthesized for Zynq UltraScale+, the design uses 74k LUTs, 38k flip-flops and 175 DSPs, requiring 190k/383k cycles for signature generation and 7.8k/16.6k cycles for verification. Compared to existing partial implementations, our accelerator achieves lower resource utilization while supporting both operations, and with all source code publicly available.

• Language: English
• Keywords: Falcon, post-quantum cryptography, digital signature, FPGA, lattice-based cryptography, SystemVerilog
• Work type: Master's thesis/paper
• Typology: 2.09 - Master's Thesis
• Organization: FRI - Faculty of Computer and Information Science
• Year: 2025
• PID: 20.500.12556/RUL-175963
• COBISS.SI-ID: 258122755
• Publication date in RUL: 14.11.2025

Secondary language

• Language: Slovenian
• Title: Strojna implementacija post-kvantne podpisne sheme Falcon

Abstract

Kvantni računalniki ogrožajo sedanje algoritme za digitalno podpisovanje, zato je NIST standardiziral več post-kvantnih alternativ, med njimi tudi Falcon. Ta uporablja aritmetiko s plavajočo vejico in rekurzivne algoritme, kar otežuje načrtovanje učinkovitih strojnih implementaciji. To magistrsko delo predstavlja prvi enotni pospeševalnik za generiranje in preverjanje podpisov za Falcon-512 in Falcon-1024, ki je v celoti izveden v strojni opremi. Sintetiziran za arhitekturo Zynq UltraScale+ uporablja 74k LUT-ov, 38k flip-flopov in 175 DSP-jev, za generiranje podpisov potrebuje 190k/383k ciklov, za preverjanje pa 7,8k/16,6k ciklov. V primerjavi z obstoječimi implementacijami posameznih algoritmov naš pospeševalnik dosega nižjo porabo virov, hkrati pa podpira obe operaciji. Vsa izvorna koda je javno dostopna.

• Keywords: Falcon, post-kvantna kriptografija, digitalni podpis, FPGA, kriptografija na osnovi rešetke, SystemVerilog