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Načrtovanje popolnoma diferencialnega ojačevalnika za gigabitni Ethernet oddajnik
ID Huč, Katarina (Author), ID Pečar, Borut (Mentor) More about this mentor... This link opens in a new window

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Abstract
Diplomsko delo se osredotoča na načrtovanje popolnoma diferencialnega operacijskega ojačevalnika (OTA), namenjenega za uporabo v gigabitnem Ethernet oddajniku. Ojačevalnik mora izpolnjevati stroge zahteve po ojačanju, stabilnosti in pasovni širini. Predvidena je dvostopenjska topologija z vhodno teleskopsko ter izhodno invertersko stopnjo. Pri načrtovanju bo uporabljena metodologija gm/I_d za določanje razmerij med tokovi in dimenzijami tranzistorjev ter za določitev U* vrednosti posameznih vej. Po opravljenih izračunih bo vezje simulirano v okolju Cadence z uporabo standardnih testnih vezij. Z analitičnim in simulacijskim pristopom bo mogoče raziskati vpliv najpomembnejših načrtovalskih parametrov na delovanje ojačevalnika, kar je ključnega pomena pri razvoju analognih gradnikov za visoko zmogljive komunikacijske sisteme.

Language:Slovenian
Keywords:diferencialni opeacijski ojačevalnik, gm/I_d metodologija, dimenzioniranje tranzistorjev, Cadence
Work type:Bachelor thesis/paper
Typology:2.11 - Undergraduate Thesis
Organization:FE - Faculty of Electrical Engineering
Year:2025
PID:20.500.12556/RUL-171438 This link opens in a new window
COBISS.SI-ID:248110851 This link opens in a new window
Publication date in RUL:26.08.2025
Views:472
Downloads:186
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Secondary language

Language:English
Title:Design of a Fully Differential Amplifier for a Gigabit Ethernet Transceiver
Abstract:
The thesis focuses on the design of a fully differential operational transconductance amplifier (OTA) intended for use in a gigabit Ethernet transmitter. The amplifier must meet stringent requirements in terms of gain, stability, and bandwidth. A two-stage topology is proposed, consisting of a telescopic input stage and an inverting output stage. For determining the ratios between currents and transistor dimensions, as well as to define the V* values of individual branches, the gm/I_d methodology will be employed. Following the design calculations, the circuit will be simulated using Cadence simulation environment with standard test configurations. By combining analytical and simulation-based approaches, the thesis aims to provide a thorough understanding of how individual design parameters affect amplifier performance — an essential aspect in the development of analog components for high-performance communication systems.

Keywords:differential operational amplifier, gm/I_d methodology, transistor sizing, Cadence

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