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Digitalno-časovni pretvornik visoke ločljivosti v vezju FPGA
ID Šuligoj, Jan (Author), ID Trost, Andrej (Mentor) More about this mentor... This link opens in a new window

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Abstract
V tem magistrskem delu sem se lotil izdelave digitalno-časovnega pretvornika, ki temelji na programirljivem polju vrat. Cilj magistrskega dela je raziskati, implementirati in izmeriti različne načine digitalno-časovnih pretvornikov, realiziranih v vezjih programirljivega polja vrat. Končni cilj je na najprimernejši način implementirati digitalno-časovni pretvornik v vezje za krmiljenje laserskega ojačevalnika z visoko časovno ločljivostjo. Vsi izdelani digitalno-časovni pretvorniki so popolnoma digitalni in implementirani na čipu Zynq 7010 proizvajalca Xilinx. V sklopu magistrskega dela sem izdelal in preizkusil delovanje zakasnilnih linij, sestavljenih iz elementov CARRY4, blokov DSP48 in vgrajenih modulov za zakasnitve IDELAYE2. Zahtevana ločljivost, potrebna za krmiljenje laserskega ojačevalnika, je znašala 100 ps, največja zakasnitev pa kar 100 us. Vsi omenjeni načini omogočajo zakasnitve le za nekaj nanosekund, zato je digitalno-časovni pretvornik sestavljen iz dveh delov, in sicer števca za grobo nastavljanje zakasnitve ter zakasnilne linije, izdelane z eno izmed omenjenih metod, ki skrbi za časovne intervale, krajše od periode števca. V končni aplikaciji morajo biti zakasnitve sinhronizirane z uro z laserskega vira s tipično frekvenco 20–50 MHz. Zakasnitve so prosto programirljive prek naprednega razširljivega vmesnika, ki povezuje procesorski del čipa z logičnim.

Language:Slovenian
Keywords:časovno-digitalni pretvornik, programirljiva vezja, FPGA, zakasnilna linija, prenosna logika, visoka ločljivost
Work type:Master's thesis/paper
Typology:2.09 - Master's Thesis
Organization:FE - Faculty of Electrical Engineering
Year:2024
PID:20.500.12556/RUL-163819 This link opens in a new window
COBISS.SI-ID:217472771 This link opens in a new window
Publication date in RUL:11.10.2024
Views:102
Downloads:30
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Secondary language

Language:English
Title:High-resolution digital-to-time converter in an FPGA circuit
Abstract:
In the master's thesis, I developed a digital-to-time converter (DTC) based on a field programmable gate array (FPGA). The aim of the work is to investigate, implement and measure different modes of DTCs implemented in FPGA circuits. The final goal is the most convenient way to implement into the circuit to control the laser amplifier with high time resolution. All developed digital-to-time converters are fully digital and implemented on Xilinx's Zynq 7010 chip. As part of master's thesis, I designed and tested the operation of delay lines consisting of CARRY4 elements, DSP48 blocks and built-in IDELAYE2 delay modules. The required resolution needed to control the laser amplifier was 100 ps, and the maximum delay was 100 us. All the abovementioned methods allow a delay of only a few nanoseconds, so the DTC consists of two parts: a counter for coarse delay setting, and a delay line built with one of the abovementioned methods, which takes care of time intervals shorter than the period of the counter. In the target application, the delays must be synchronized to the clock from a laser source, which is typically between 20 and 50 MHz. The delays are freely programmable via the AXI interface, which connects the processor part of the chip to the logic part.

Keywords:time-to-digital converter, programmable logic, FPGA, delay line, portable logic, high resolution

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