Master thesis contains loss and efficiency analysis of the RFID system output.
We studied the circuit operation and efficiency at reduced gate voltages of the
output power transistors by separating the power supply of the PMOS and NMOS
transistors. We also tested the circuit operation at higher driver voltages. Due to
the higher driver voltages, the control voltages must be lower, since high-voltage
transistors are controlled with a lower voltage compared to the voltage of the
driver or load. With higher driver voltage, we can achieve higher load voltages
(in our case, an ohmic load and an antenna with a matching circuit).
We determined the power losses of the driver and the gate charging power
of the driver power transistors at different driver and control circuit voltage settings. By separating the control voltage, we achieved higher output power, higher
efficiencies at higher powers and lower losses at lower output powers, depending
on the voltage setting. We conducted the efficiency analysis with an ohmic load
and a real antenna with a matching circuit and obtained similar results with
both types of loads. All simulations were performed with the Cadence software
package [1].
This work confirms that the use of a separate power supply for the output
circuit control part makes sense in certain voltage settings and output power
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