Analiza in testiranje programirljivega manipulatorja bitov za razvoj komunikacijskih vmesnikov

Ogorevc, David (author), Perš, Janez (mentor)

Magistrsko delo se je posveˇceno testiranju in evaluaciji manipulatorja bitov, ki temelji na programirljivem digitalnem vezju. Raziskovali smo njegovo primernost za razvoj in testiranje komunikacijskih vmesnikov ter ˇzeleli oceniti uˇcinkovitost vpeljave in uporabe takˇsnega sistema. Analizirali smo zmogljivosti manipulatorja bitov in preverjali, ali smo uspeˇsno implementirali komunikacijski nadzornik, ki temelji na programirljivih digitalnih vezjih. Osredotoˇcili smo se na izpolnjevanje osnovnih zahtev in delovanje komunikacijskega nadzornika za komunikacijski protokol zaporednega perifernega vmesnika SPI. Testirali smo tudi razvojno okolje in komunikacijske moˇznosti nadzornika z osebnim raˇcunalnikom za prenos podatkov. Naˇsi rezultati kaˇzejo, da manipulator bitov deluje hitro in je ustrezen za razvojne potrebe v podjetju. Uporaba analiziranega manipulatorja bitov, ki temelji na programirljivih digitalnih vezjih, ne zahteva specifiˇcnih programerskih veˇsˇcin za delo s takˇsnimi vezji. Kljub potrebi po dodatnem razvoju manipulator bitov ˇze zdaj nudi lastnosti, ki inˇzenirjem olajˇsajo razvoj dajalnikov pozicije.

• Language: Slovenian
• Keywords: manipulator bitov, FPGA, bit banger, komunikacijski nadzornik, master
• Work type: Master's thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2023
• PID: 20.500.12556/RUL-152079-310fdd62-9fd3-47e3-58df-cc570c961309
• COBISS.SI-ID: 181004547
• Publication date in RUL: 02.11.2023

Secondary language

• Language: English
• Title: Analysis and Testing of FPGA-Based Bit Manipulator for Development of Communication Interfaces

Abstract

The master thesis is dedicated to the testing and evaluation of a bit banger based on a Field-programmable gate array. We investigated its suitability for the development and testing of communication interfaces and wanted to evaluate the effectiveness of the implementation and use of such a system. We analysed the performance of the bit banger and verified the successful implementation of a communication controller based on Field-programmable gate array. We focused on the fulfilment of the basic requirements and the performance of the communication master for the SPI serial peripheral interface communication protocol. We also tested the development environment and the communication capabilities of the master with a PC for data transfer. Our results show that the bit banger is fast and suitable for the development needs of an enterprise. The use of the analysed bit banger based on Fieldprogrammable gate array does not require specific programming skills to work with such circuits. Despite the need for further development, the bit banger already offers features that facilitate the development of position encoders by engineers.

• Keywords: bit banger, Field-programmable gate array, FPGA, communication master