Vrednotenje zmogljivosti mikrokrmilnikov družine AURIX

Kolšek, Mojca (author), Šter, Branko (mentor), Verderber, Matjaž (comentor)

Cilj magistrske naloge je bil ovrednotenje zmogljivosti dveh družin mikrokrokrmilnikov AURIX podjetja Infineon. Mikrokrmilniki AURIX se pogosto uporabljajo v avtomobilski industriji, ki ima visoke varnostne zahteve in omejitve. Vloga mikrokrmilnikov je krmiljenje zunanjih naprav, kar jih postavlja v realno-časovno okolje. Vrednotenje zmogljivosti je zato koristno orodje pri načrtovanju sistemov in nam lahko pomaga pri nakupu ali razvoju ustrezne strojne in programske opreme. Mikrokrmilniki družine AURIX uporabljajo centralne procesne enote (CPE) TriCore. Znotraj prve in druge generacije so na voljo tri različne implementacije jeder; 1.6E, 1.6P in 1.6.2P. Poleg vrednotenja zmogljivosti treh jeder smo opazovali tudi zmogljivost podatkovnih pomnilnikov, ki so nam bili na voljo: DFlash, DSPR in DLMU. Opazovali smo tudi vpliv uporabe predpomnilnika. Na treh jedrih smo opravili časovne meritve za devet pogosto uporabljenih operacij. Za vsako operacijo smo izmerili pretočnost v različnih merilnih okoljih, ki jih določajo tri opazovane spremenljivke. Vpliv spremenljivk na pretočnost smo vrednotili s pomočjo trosmernega testa ANOVA, ki je potrdil znaten vpliv posameznih spremenljivk in visoko stopnjo interakcij med njimi. S pomočjo dvosmernega testa ANOVA, testa Kruskal-Wallis in Welchovega t-testa smo opazovali interakcijo med spremenljivkami in bolj podrobno primerjali pretočnosti pri uporabi lastnega in tujega pomnilnika DSPR ter pretočnosti pri uporabi pomnilnikov DSPR in DLMU. Analiza je pokazala, da je najmanj zmogljivo jedro 1.6E, medtem ko sta jedri 1.6P in 1.6.2P skoraj enako zmogljivi. Najbolj pretočni so lastni pomnilniki (DSPR in DLMU). Tuji pomnilniki lahko v najboljšem primeru dosežejo pretočnost lastnih, če omogočimo pisanje v predpomnilnik. Rezultati odražajo razlike med jedri, pomnilniki in predpomnilniki, ki so zapisane v uporabniških priročnikih.

• Language: Slovenian
• Keywords: zmogljivost, mikrokrmilnik, AURIX, TriCore, pretoˇcnost, podatkovni pomnil- nik, predpomnilnik
• Work type: Master's thesis/paper
• Typology: 2.09 - Master's Thesis
• Organization: FRI - Faculty of Computer and Information Science
• Year: 2022
• PID: 20.500.12556/RUL-143690
• COBISS.SI-ID: 138656003
• Publication date in RUL: 09.01.2023

Secondary language

• Language: English
• Title: Performance evaluation of AURIX microcontroller family

Abstract

The goal of this master thesis was to evaluate two generations of microcontrollers from AURIX family by Infineon. Their microcontrollers are often used in the automotive industry, which has high safety requirements. In automotive applications, microcontrollers often control and sense their environment through actuators and sensors. They are therefore a part of real-time environment. Performance evaluation is thus a useful tool for system planning and can aid in hardware purchase or development. The AURIX Family uses TriCore CPUs. First generation includes implementations 1.6E and 1.6P while the second generation implements core 1.6.2P. Along with performance evaluation of different cores we decided to analyze performance of data memory sections that were available and the influence of cache memory use. We completed time measurements of nine often used operations. We measured time needed to complete the operations in different environments determined by the three variables; CPU implementation, data memory used and availability of cache use. We evaluated the influence of variables on throughput per operation with three-way ANOVA that confirmed significant influence from individual variables as well as a great influence from variable interactions. We furthermore used two-way ANOVA, Kruskal-Wallis test and Welch's t-test to gain more insight in interactions discovered with three-way ANOVA and with help of AURIX user manuals. We compared DSPR memory with DLMU memory and local DSPR memory with its global pair. The analysis deemed core 1.6E as least efficient while it reviled that cores 1.6P and 1.6.2P are similarly efficient. We found local DSPR and DLMU memories are more efficient than any other evaluated data memory although global DSPR and/or DLMU memory can match throughput of their local pairs when enough cache memory is available. The results reflect differences between core implementations, data memory and data cache implementations and changes of memory architectures between the generations that are noted in the user manuals.

• Keywords: performance, microcontroller, AURIX, TriCore, throughput, data memory, cache memory