A binary neural network on an FPGA

LANGERHOLC, KLARA (author), Lotrič, Uroš (mentor), Seog Han, Dong (comentor)

In recent years, the performance of convolutional neural networks has been increasing rapidly. But higher performance brings higher computational and memory costs. Research has shown that good accuracy can be achieved even when operands are constrained to only one or two bits. The purpose of this work is to implement a binary neural network with operands constrained to one bit on a field-programmable gate array. The computations in binary neural networks are mostly binary, while the weights require very little memory, making them ideal for hardware implementation. The implemented network was tested on MIO-TCD database, while the implementation was mostly focused on resource consumption and speed.

• Language: English
• Keywords: binary neural network, FPGA, Verilog, ZedBoard
• Work type: Bachelor thesis/paper
• Typology: 2.11 - Undergraduate Thesis
• Organization: FRI - Faculty of Computer and Information Science
• Year: 2020
• PID: 20.500.12556/RUL-120151
• COBISS.SI-ID: 32142083
• Publication date in RUL: 16.09.2020

Secondary language

• Language: Slovenian
• Title: Binarna nevronska mreža na programirljivem vezju FPGA

Abstract

V zadnjih letih se zmogljivosti konvolucijskih nevronskih mrež neprestano povečujejo. Vendar pa se z zmogljivostjo povečuje tudi kompleksnost mrež in s tem poraba računskih virov in virov za shranjevanje uteži. Raziskave so pokazale, da je pri mnogih problemih zadovoljivo delovanje nevronskih mrež doseženo tudi z le enobitnimi ali dvobitnimi operandi. V tem delu smo binarno konvolucijsko mrežo implementirali na reprogramirljivem vezju FPGA. Računske operacije v binarnih mrežah so večinoma binarne, za shranjevanje uteži pa se potrebuje malo prostora, kar jih naredi idealne za implementacijo v strojni opremi. Implementirano mrežo smo testirali na bazi slik MIO-TCD, pri imlementaciji pa smo bili pozorni predvsem na porabo virov in hitrost izvedbe.

• Keywords: binarna nevronska mreža, FPGA, Verilog, ZedBoard