Pospeševanje množenja matrik z vezjem FPGA in razvojnim okoljem Vitis

Ljubotina, Miloš (author), Žemva, Andrej (mentor), Biasizzo, Anton (comentor)

Namen tega dela je ovrednotiti programsko okolje Vitis Unified Software Platform za pospeševanje opravil, kot je množenje matrik. V vezju FPGA na razširitveni kartici PCI-e v gostiteljskem računalniku je z omenjenim orodjem implementiran sistem za množenje matrik. Njegova zmogljivost je primerjana z zmogljivostmi dveh obstoječih rešitev, Vitis BLAS in Intel MKL. Primerjava temelji na izmerjenih hitrostih izvajanja operacij. Sistem je implementiran za razširitveno kartico Alveo U250 Data Center. Njegov načrt temelji na sistoličnem polju za množenje matrik, koristi 16-bitno aritmetiko s fiksno vejico in podpira matrike do velikosti 1024 x 1024. Zaradi količine neuporabljenih sredstev po implementaciji je realiziran še drug sistem z dvema identičnima cevovodoma. Njegove arhitekturne značilnosti so enake, a deluje pri malo nižji frekvenci in podpira vršenje dveh operacij hkrati. Zaradi težav s knjižnico Vitis BLAS je za primerjavo uporabljena le knjižnica Intel MKL. Njena zmogljivost množenja matrik z 32-bitnim podatkovnim tipom s plavajočo vejico je izmerjena na Intelovih procesorjih: i7 4700HQ, Xeon Gold 6144, Xeon Gold 6154 in Xeon Platinum 8180. Rezultati kažejo v prid implementiranih sistemov, a je treba upoštevati, da se uporabljen podatkovni tip razlikuje. Bistvo je, da je zmogljivost primerljiva in programsko okolje Vitis zmore proizvesti uporabne rezultate.

• Language: Slovenian
• Keywords: programirljivo polje logičnih vrat, množenje matrik, Vitis Unified Software Platform, sistolično polje, pospeševanje algoritmov, načrtovanje digitalnih vezij
• Work type: Master's thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2020
• PID: 20.500.12556/RUL-120062
• Publication date in RUL: 15.09.2020

LJUBOTINA, Miloš, 2020, Pospeševanje množenja matrik z vezjem FPGA in razvojnim okoljem Vitis [online]. Master’s thesis. [Accessed 26 April 2025]. Retrieved from: https://repozitorij.uni-lj.si/IzpisGradiva.php?lang=eng&id=120062

Secondary language

• Language: English
• Title: Acceleration of matrix multiplication with FPGA device and Vitis development tool

Abstract

The intent of this work is to evaluate the Vitis Unified Software Platform development environment for acceleration of tasks alike matrix multiplication. For that, a system for multiplying matrices is implemented in an FPGA device on a PCI-e extension card in a host computer with the aforementioned development tools. The system's performance is compared with the performance of two existing solutions, Vitis BLAS and Intel MKL. The basis for the comparison are the measured speeds of execution. The system is implemented for the Alveo U250 Data Center accelerator card. Its design is based on a systolic array for matrix multiplication, utilises 16-bit fixed point arithmetic and supports sizes of matrices up to 1024 x 1024. Due to the amount of unused resources after implementation, a second system with two identical pipelines is implemented. Its architectural characteristics are the same, but it operates at a slightly lower frequency and supports execution of two operations in parallel. Due to complications with the Vitis BLAS library, only the Intel MKL library is used for comparison. Its 32-bit floating point matrix multiplication performance is measured on Intel processors: i7 4700HQ, Xeon Gold 6144, Xeon Gold 6154, and Xeon Platinum 8180. The results favor the implemented systems, however the data type used is different. The key takeaway is that the performance is comparable and the Vitis development platform is able to provide useful results.

• Keywords: field-programmable gate array, matrix multiplication, Vitis Unified Software Platform, systolic array, algorithm acceleration, digital circuit design