Strojna izvedba konvolucijske nevronske mreže na programirljivem vezju

Ipavec, Domen (author), Trost, Andrej (mentor)

YOLO je algoritem za prepoznavanje in določanje lokacije predmetov na slikah. Za to uporablja konvolucijske nevronske mreže. Je računsko precej zahteven, zato bi radi zanj izkoristili FPGA vezja. V magistrski nalogi je opisana implementacija algoritma v jeziku C++ z uporabo visoko nivojske sinteze. Primerjana sta hitrost algoritma na procesorju ARM in v FPGA vezju. Prav tako so raziskani učinki uporabe različne velikosti podatkovnih tipov za računanje. Z uporabo števil z nepremično decimalno vejico velikosti 24-bitov, ki so optimalna, dosežemo na majhnem FPGA vezju na ZedBoard-u, bistveno hitrejšo implementacijo kot na primerljivem procesorskem sistemu.

• Language: Slovenian
• Keywords: Konvolucijske nevronske mreže, YOLO, FPGA, HLS
• Work type: Master's thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2018
• PID: 20.500.12556/RUL-104078
• Publication date in RUL: 04.10.2018

Secondary language

• Language: English
• Title: Hardware implementation of convolutional neural network on programmable device

Abstract

YOLO is a system for detection and localization of objects in images using convolutional neural networks. It is computationally intensive, so we want to use FPGAs for better performance. This master's thesis describes the implementation of the algorithm in C++ using high level synthesis. The speed of the algorithm is compared between software implementation on ARM processor and the FPGA. The effects of using different data types and sizes on computation are also explored. Using 24 bit fixed point numbers, that are optimal, on the small FPGA chip available on ZedBoard, we can achieve significantly faster implementation than a comparable processor system.

• Keywords: Convolutional neural networks, YOLO, FPGA, HLS