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Testne strukture za simulacijo digitalnih vezij
ID KURMANŠEK, TOMAŽ (Author), ID Trost, Andrej (Mentor) More about this mentor... This link opens in a new window

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MD5: E4F6C0EF089FC0D550F7086BF8871882
PID: 20.500.12556/rul/b30bd4cb-198b-4f79-902e-3138ff5c31cf

Abstract
Za simulacijo digitalnih vezij se uporabljajo različni pripomočki. Kot eden najučinkovitejših orodij, se je pokazala testna struktura. Za opis testnih struktur in modelov vezij se uporablja različne jezike. Kot najbolj pogosto uporabljena sta VHDL in Verilog. Te jezike uporabljamo takrat, ko postane vezje kompleksno in shematski opis ni več primeren. Vezja se med seboj razlikujejo in naloga zajema različna vezja. Z njimi se predstavi različne načine pisanja testnih struktur. Ker je največja razlika med vezji glede načina delovanja, je ločeno predstavljen potek in razlika simulacije kombinacijskih in sekvenčnih gradnikov. Kako se tesna struktura lahko razvije in kaj omogoča, je podrobno prikazano pri testiranju serijskega vmesnika RS232.

Language:Slovenian
Keywords:testna struktura, VHDL, kompleksna vezja, sekvenčna vezja, RS232
Work type:Undergraduate thesis
Organization:FE - Faculty of Electrical Engineering
Year:2016
PID:20.500.12556/RUL-85501 This link opens in a new window
Publication date in RUL:15.09.2016
Views:1603
Downloads:252
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Secondary language

Language:English
Title:Testbenches for digital circuit simulation
Abstract:
There are different accessories which are used to simulate digital circuits. A test bench is one of the most effective tools. Different languages are used for a description of the test benchs and models of circuits. The most commonly used are VHDL and Verilog. These languages are used when the circuit becomes complex and schematic description is no longer appropriate. Circuits differ from each other. The thesis contains various circuits which are used to present different ways of writing the test benches. The biggest difference between the circuits is the mode of working hence the course and the difference in simulation of combinational and sequential blocks are separately presented. How the test bench can be developed and what it offers is shown in detailed examples of the serial interface RS232.

Keywords:test bench, VHDL, complex circuits, sequential circuits, RS232

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