Cevovodni procesor HIP v vezju FPGA z okoljem za razhroščevanje

LAPAJNE, DAVID (author), Bulić, Patricio (mentor)

Diplomska naloga obsega implementacijo cevovodne centralne procesne enote imenovane hipotetični procesor (HIP), narejen po principih opisanih v knjigi [1]. Vsebuje logiko za premoščanje, seštevalnik števil zapisanih v plavajoči vejici. Dodan ima ukazni in podatkovni predpomnilnik. Preko razhroščevalne enote je mogoče brati vse splošnonamenske in vmesne registre v cevovodu HIP ter tako spremljati izvajanje poteka prevedenega programa. HIP se izvaja na FPGA čipu na razvojni ploščici Spartan 3E, kjer se nahaja podporno vezje za nadzor in komunikacijo. Zunanji program, napisan v Javi, je možno pognati na različnih operacijskih sistemih. V razhroščevalniku je možno pisati program v zbirnem jeziku. Vsebuje prevajalnik iz zbirnega v strojni jezik. Strojno kodo poganja tako, da v razhroščevalno enoto v HIP pošilja ukaze in podatke, ki so potrebni za izvajanje. Pri izvajanju se vsako urino periodo prebere vsebina registrov v CPE. Vidna je tudi vsebina glavnega pomnilnika in predpomnilnika.

• Language: Slovenian
• Keywords: HIP, ANTLR, VHDL, zbirni jezik, prevajalnik, razčlenjevalnik, razhroščevalnik, FPGA
• Work type: Undergraduate thesis
• Organization: FRI - Faculty of Computer and Information Science
• Year: 2016
• PID: 20.500.12556/RUL-84940
• Publication date in RUL: 08.09.2016

Secondary language

• Language: English
• Title: The pipelined HIP processor in FPGA with the debugging environment

Abstract

This thesis describes the implementation of a central processing unit with pipeline called Hypothetical processor (HIP), which is described in book [1]. It contains logic for data forwarding, an adder for floating point numbers and it has an instruction and data cache. Through the debug unit it is possible to read from and write to all general and to other registers in the HIP pipeline and therefore monitor the flow of the compiled program. HIP runs in the FPGA chip on the Spartan 3E development board where supporting logic for monitoring is present. The external program written in Java runs on different operating systems. The monitoring program contains a text editor where it is possible to write in the assembler language. It also contains a compiler which translates an assembler code to HIP machine code. Operations and data are sent to the debug unit to HIP. Each clock cycle, the monitoring program reads the content of every register in the CPU. The content of the main memory and cache is seen too.

• Keywords: HIP, ANTLR, VHDL, assembler, compiler, parser, debugger, FPGA