The master's thesis describes design, simulation and optimization a schematic for an integrated analog digital converter designed in 350 nm technology.
The converter has 10 bit resolution and a speed of 13.3 mega samples per seconds. It uses 1.7 mW of power when operating at the maximum frequency. To decrease the
number of input pins the converters implements serialization logic for the digital output. A key component in SAR converters is an integrated digital to analog converter,
it creates known analog values to which the unknown sampled value is compared. Owing to its importance a significant amount of the masters thesis was spent on the design and
optimization of this component. Multiple different digital to analog converters were tried (Capacitive ladder, Current steering, Resistor ladder).
To lower the parasitic characteristics of the integrated components a floating voltage shield was used.
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