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Razvoj sistema za obdelavo video toka z nizko latenco
ID GANIĆ, LUKA (Author), ID Ilc, Nejc (Mentor) More about this mentor... This link opens in a new window, ID Pilipović, Ratko (Comentor)

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Abstract
V diplomski nalogi je opisan pristop k procesiranju slike z uporabo arhitekture UltraScale+ podjetja AMD Xilinx. Na praktičnem primeru je predstavljena uporaba heterogenega sistema, ki zajema visoko-prepustni vhod/izhod, grafično procesno enoto in programirljivo polje logičnih vrat FPGA. Preučevanje sistema in reševanje problema je potekalo v dveh delih. Najprej je bila potrebna vzpostavitev cevovoda slike: zajem slike, shranjevanje slike in prikaz na standardnem izhodu. V drugem delu je bilo razvito jedro IP, ki lahko na zaslon izriše različne geometrijske like in izvaja barvne manipulacije video toka. Rezultati so pokazali, da je lahko s pomočjo sistema na čipu dosežena zakasnitev obdelave video toka, manjša od ene milisekunde. Programirljivo vezje se je ob sodelovanju s procesorskim sistemom izkazalo za izjemno hitro in energetsko učinkovito orodje za obdelavo video toka.

Language:Slovenian
Keywords:obdelava video toka, sistem na čipu, FPGA
Work type:Bachelor thesis/paper
Typology:2.11 - Undergraduate Thesis
Organization:FRI - Faculty of Computer and Information Science
Year:2024
PID:20.500.12556/RUL-162598 This link opens in a new window
COBISS.SI-ID:214394371 This link opens in a new window
Publication date in RUL:25.09.2024
Views:110
Downloads:44
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Secondary language

Language:English
Title:Development of a low-latency video stream processing system
Abstract:
The thesis describes the approach to image processing using the UltraScale+ architecture of AMD Xilinx. On a practical example, the use of a heterogeneous system of the latter architecture is presented, including a high-pass input / output, a graphic processing unit and a programmable logic port field FPGA. The research of the system and the solution of the problem took place in two parts. First, it was necessary to establish an image pipeline, i.e. image capture, image storage, and display on standard output. Second, we created custom IP core capable of drawing different shapes and performing color manipulation of a data stream. Results showed that we can achieve latency smaller than one milisecond when performing video stream processing on a system on chip. The programmable circuit, in cooperation with the processing system, has proven to be an extremely fast and energy-efficient tool for video stream processing.

Keywords:video stream processing, system on a chip, FPGA

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