This Master thesis focuses on the development and implementation of an FPGA-based data acquisition system. The thesis provides an overview and analysis of existing data acquisition systems, presenting the different types of systems, their functionalities, acquisition speed, memory solutions and connectivity to external devices.
A demonstration data acquisition system has been developed on the XEM7310-A200 development board, which includes an analogue-to-digital converter, an external SDRAM memory and a USB 3.0 interface for data transfer. The system was implemented using the Vivado tool in the Verilog hardware-description language. It consists of four modules: an analogue-to-digital data acquisition module, a data write control module, a module for interacting with the SDRAM memory interface and a top module which interfaces all the above modules and the IP cores used: two FIFO registers, a MIG memory interface, an XADC analogue-to-digital converter, a FrontPanel computer interface and a clock clocking wizard generator. In addition, we have implemented software that allows data transfer between the FPGA and the computer. After the transfer, the data is written to a .csv file where it is available to the user for further processing. The system captures the value of the analogue input voltage using a 12-bit analogue-to-digital converter at 500 kHz.
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