Visokonivojska sinteza vezij za obdelavo video signala na programirljivih napravah

Babnik, Tilen (avtor), Žemva, Andrej (mentor), Trost, Andrej (komentor)

Diplomsko delo se osredotoča na visokonivojsko sintezo algoritmov za obdelavo video signalov, prilagojenih za programirljiva FPGA vezja. Natančneje, delo obravnava razvoj in sintezo algoritma za linearno lokalno obdelavo video signala, z uporabo visokonivojskega jezika C++. Nastali algoritem je prilagojen v tri različna linearna lokalna sita, ki so nato implementirana na FPGA vezje razvojne plošče MiniZed. Primarni cilj te diplomske naloge je izkoristiti zmogljivosti C++ za ustvarjanje vsestranskega algoritma, ki ga je mogoče enostavno sintetizirati v različna linearna lokalna sita z manjšimi prilagoditvami osnovne C++ kode. Uvodni del podaja pregled uporabe visokonivojske sinteze pri razvoju in oblikovanju digitalnih vezij za implementacijo na FPGA vezja. Na kratko je obravnavana arhitektura in razpoložljiva sredstva FPGA, za izvajanje sistemov video obdelave. V nadaljevanju je obravnavana uporaba orodja Vivado HLS, s poudarkom na optimizacijskih metodah in direktivah, uporabljenih v tem delu, za izdelavo linearnega lokalnega algoritma za obdelavo slik. Razvoj algoritma je opisan v dveh poglavjih. Prvo poglavje obravnava ustvarjanje in sintezo algoritma za predpomnjenje slikovnih točk z uporabo dveh različnih pristopov. Prvi pristop uporablja pomnilnike BRAM, drugi pa uporablja pomikalne registre. V obeh primerih zasnovana algoritma zagotavljata prilagodljivost, saj omogočata enostavno prilagajanje velikosti okna in dimenzij obdelane slike. Rezultate sinteze so nato analizirani in primerjani med obema pristopoma. Naslednje poglavje se osredotoča na algoritem za izračun konvolucije, ki je prav tako zasnovan za omogočanje enostavnih sprememb funkcionalnosti. Ta algoritem je v nadaljevanju prilagojen za implementacijo treh različnih linearnih lokalnih sit za zaznavanje robov, glajenje in ostrenje slike. Rezultati sinteze na koncu pokažejo, da ciljno FPGA vezje ni zmožno implementirati sit za večino standardnih prikazov VGA. Na koncu so razviti algoritmi sintetizirani in implementirani na ciljno FPGA vezje. Kljub obetavnim rezultatom med sintezo, ki kažejo na ustreznost sintetizirane RTL arhitekture, večina sit med dejansko implementacijo ne izpolnjuje zahtevanih časovnih omejitev.

• Jezik: Slovenski jezik
• Ključne besede: HLS, FPGA, sinteza, RTL arhitektura, lokalna sita, slikovna točka, konvolucija, VGA
• Vrsta gradiva: Diplomsko delo/naloga
• Organizacija: FE - Fakulteta za elektrotehniko
• Leto izida: 2023
• PID: 20.500.12556/RUL-150755
• COBISS.SI-ID: 166799107
• Datum objave v RUL: 22.09.2023

Sekundarni jezik

• Jezik: Angleški jezik
• Naslov: High-level synthesis of video signal processing circuits on programmable devices

Izvleček

This thesis focuses on the high-level synthesis of video processing algorithms tailored for programmable FPGA circuits. Specifically, it addresses the development and synthesis of an algorithm for linear local video signal processing using the high-level language C++. The resulting algorithm is then adapted into three distinct linear local filters, which are subsequently implemented on the FPGA circuit of the MiniZed development board. The primary aim of this thesis is to exploit the capabilities of C++ to create a versatile algorithm that can be easily synthesized in a variety of linear local filters with minor modifications to the base C++ code. The introductory part of this thesis provides an overview of the use of high-level synthesis in the development and design of digital circuits for FPGA implementation. Next, the FPGA circuit architecture and available resources for implementing video processing systems is briefly discussed. Furthermore, the thesis describes the use of the Vivado HLS tool, focusing on the optimization methods in the directives used in this work, to implement a linear local algorithm for image processing. The development of the algorithm is described in two chapters. The first chapter deals with the generation and synthesis of a pixel caching algorithm using two different approaches. The first approach uses BRAM memory and the second approach uses a shift register. In both cases, the designed algorithm ensures flexibility, as it allows easy adjustment of the window size and the dimensions of the image being processed. The synthesis results are then analyzed and compared between the two approaches. The next chapter focuses on the algorithm for calculating the convolution, which is also designed to allow easy changes to its functionality. This algorithm is subsequently adjusted to implement three different linear local filters for edge detection, smoothing and sharpening of images. In the end, the synthesis results show that the target FPGA circuit is not capable to implement a local filter for most of the standard VGA displays. Finally, the developed algorithms are synthesized and implemented on the target FPGA circuit. Despite the promising result during synthesis, which shows the adequacy of the synthesized RTL architecture, most of the filters do not meet the required time constraints during actual implementation.

• Ključne besede: HLS, FPGA, synthesis, RTL architecture, local filter, pixel, convolution, VGA