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Načrtovanje digitalnih vezij z visokonivojsko sintezo
ID Šuligoj, Andraž (Author), ID Trost, Andrej (Mentor) More about this mentor... This link opens in a new window

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Abstract
Zaradi naraščajoče kompleksnosti digitalnih vezij se težnja po lažjem načrtovanju veča. Skozi leta se je za načrtovanje digitalnih vezij najbolj uveljavilo RTL-modeliranje, in sicer s pomočjo strojno opisnih jezikov. Zaradi želje po še hitrejšem razvoju in verifikaciji, se je razvila visokonivojska sinteza, ki načrtovalcu omogoča opis digitalnega vezja s programskim jezikom. Skozi diplomsko delo je predstavljeno delovanje visokonivojskega prevajalnika, nato je skozi več algoritmov prikazan postopek načrtovanja digitalnega vezja z uporabo visokonivojske sinteze. Skozi opis implementacije prvega algoritma (Sobelovo sito) je prikazan učinkovit način visokonivojskega opisa, algoritmov za video obdelavo. Ta opisuje obdelavo slik z uporabo vrstičnih medpomnilnikov (angl. line buffers) in oken (angl. window buffers). V drugem delu je predstavljena implementacija grafičnega vmesnika za osciloskop, na programirljivi logiki. V delu so opisani postopki skaliranja, proženja, branja kanalov in izrisa prebranih podatkov. Med načrtovanjem, se je hitro pokazalo, da je predznanje o digitalnih vezjih in strojno opisnih jezikih pomembno, čeprav je vezje opisano s programskim jezikom. Uporabnost visokonivojske sinteze se je opazila pri hitrem razvoju in hitri verifikaciji zmogljivosti vezja, medtem ko se je pri predvidevanju zasedenosti programirljivega vezja orodje izkazalo za nezanesljivo.

Language:Slovenian
Keywords:visokonivojska sinteza, FPGA, obdelava slik, Sobelovo sito, grafični vmesnik osciloskopa
Work type:Bachelor thesis/paper
Organization:FE - Faculty of Electrical Engineering
Year:2023
PID:20.500.12556/RUL-149968 This link opens in a new window
COBISS.SI-ID:165141507 This link opens in a new window
Publication date in RUL:12.09.2023
Views:644
Downloads:111
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Secondary language

Language:English
Title:Design of digital circuits with high-level synthesis
Abstract:
Due to the increasing complexity of digital circuits, the tendency towards easier design is increasing. Over the years, RTL-modeling using hardware description languages has become the most established method for designing digital circuits. With the aim of achieving faster development and verification, high-level synthesis has been developed, allowing designers to describe digital circuits using programming languages. Throughout the thesis, the operation of a high-level compiler is presented and the process of designing a digital circuit using high-level synthesis is shown through implementation of multiple algorithms. The description of the implementation of the first algorithm (Sobel filter) demonstrates an effective way of high-level description for video processing algorithms. It describes image processing using line buffers and window buffers. In the second part, the implementation of graphical interface for an oscilloscope on programmable logic is presented. Thesis describes the procedures for scaling, triggering, reading channels and displaying acquired data. During the design process, it quickly became apparent that prior knowledge of digital circuits and hardware description languages is important, even though the algorithm itself is described using a programming language. The usefulness of high-level synthesis was noticeable in the rapid development and quick verification of circuit's performance;however, while predicting the occupancy of the programmable circuit, the tool proved to be unreliable.

Keywords:high-level synthesis, FPGA, image processing, Sobel filter, graphical interface of an oscilloscope

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