Pomnilniški vmesnik za pomnilnik DDR3 SDRAM v vezju FPGA Xilinx serije 7

BEGUŠ, JARI (author), Žemva, Andrej (mentor), Zadnik, Damjan (comentor)

Zaradi visokih kapacitet in nizke cene je pomnilnik DDR SDRAM pogosto uporabljen v vgrajenih sistemih na osnovi vezij FPGA. Za komunikacijo s pomnilnikom je v vezju FPGA potrebna implementacija pomnilniškega vmesnika, tj. vmesne plasti, ki deluje kot dvosmerni pretvornik med signali pomnilniškega čipa in aplikacijo znotraj čipa FPGA. Podjetje Xilinx za uporabo na čipih FPGA serije 7 predlaga izbiro dveh vmesnikov: Prvi je brezplačen, a zaradi svoje velikosti neprimeren za manjše čipe FPGA, drugi pa je manjši, a cenovno nedostopen. Cilj magistrske naloge je bil razvoj tretje možnosti, ki bi ob manjši zasedenosti čipa FPGA omogočala primerljive hitrosti prenosa podatkov. Delo najprej predstavi pomnilnik DDR3 SDRAM, njegovo notranjo zgradbo, zunanje povezave ter predpisan način komunikacije. V nadaljevanju so opisani v izdelanem vmesniku uporabljeni primitivi vhodno-izhodnih blokov čipa FPGA, njihov način implementacije v izdelanem vmesniku in njihovo testiranje na razvojni plošči Arty S7-50 proizvajalca Digilent s čipom FPGA iz družine Xilinx Spartan 7 in pomnilniškim čipom DDR3L x16 s kapaciteto 2 Gbit. Delo se konča z opisom delovanja pomnilniškega vmesnika, s predstavitvijo rezultatov preizkusov ter s primerjavo z že obstoječima pomnilniškima vmesnikoma. Razviti pomnilniški vmesnik DDR3 za čipe FPGA Xilinx serije 7 je bil preizkušen pri hitrosti prenosa podatkov 650 MT/s in je zasedel manj, kot 2,4 % od 8150 rezin uporabljenega čipa FPGA iz družine Spartan 7.

• Language: Slovenian
• Keywords: FPGA, DDR3 SDRAM, pomnilniški vmesnik, pomnilniški krmilnik, PHY
• Work type: Master's thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2022
• PID: 20.500.12556/RUL-141512
• COBISS.SI-ID: 125296387
• Publication date in RUL: 30.09.2022

Secondary language

• Language: English
• Title: Memory interface for DDR3 SDRAM memory in FPGA Xilinx 7 Series device

Abstract

Due to its high memory capacity and low price, DDR SDRAM is commonly used in computer and integrated systems powered both by microcontrollers and FPGAs. To communicate with external memory, an FPGA requires the implementation of a memory interface, which acts as as a two-way converter between the memory signals and the FPGA's internal logic. Xilinx, Inc. officially offers two memory interfaces for use with its 7 Series FPGAs. The first is free, but its large FPGA area usage limits it to large FPGA chips. The second has a lower FPGA utilization, but is not affordable. The goal of this thesis was to develop a third option, which would enable similar transfer speeds as the established solutions while utilizing a smaller portion of the FPGA. The thesis begins by introducing DDR3 SDRAM; Its internal structure, external connections, and its communication are discussed. The work then describes the primitives of the input-output blocks within the FPGA as used in the finished product, and the methodology employed to test them before the memory interface was developed. This was done on a Digilent Arty S7-50 development board, which houses a Xilinx Spartan 7 FPGA as well as a 2 Gbit x16 DDR3L SDRAM chip. Finally, the developed memory interface is described, along with test results and a comparison with the two memory interfaces already available. The developed DDR3 memory interface for Xilinx 7 Series FPGAs was shown to work at a memory speed of 650 MT/s while utilizing fewer than 2,4 % of the 8150 logic slices available in the used Spartan 7 FPGA device.

• Keywords: FPGA, DDR3 SDRAM, memory interface, memory controller, PHY