Implementacija procesorja RISC V na programirljivem vezju

POLJANŠEK, MATEJ (author), Trost, Andrej (mentor)

Diplomsko delo opisuje implementacijo mikroprocesorja RISC V na programirljivo vezje. Opazovali smo kompleksnost postopka, lastnosti procesorja in povezljivost perifernih enot. Za implementacijo smo izbrali odprtokodni procesor NEORV32, ki ima predpripravljen model vezja za vgradnjo na FPGA razvojno ploščo DE0-Nano. Procesor NEORV32 je bil izbran zaradi aktualne RISC V arhitekture, dobre dokumentacije in relativno enostavne zgradbe v jeziku VHDL, ki omogoča vpogled v delovanje procesorja. Model procesorja sintetiziramo z orodjem Intel Quartus Prime, kjer uporabimo predpripravljeno predlogo za implementacijo. Periferno vezje zgradimo na prototipni plošči, ki omogoča enostavno modifikacijo pri spremembi komponent. Vezje sestavlja 5 tipk, od katerih je ena namenjena zunanji prekinitveni liniji, 4 LED, matrična tipkovnica in modul za pretvorbo UART protokola v USB protokol. Kot primer kompleksne periferne komponente predstavimo priključitev razširitvene plošče z vmesnikom v jeziku VHDL, ki jo povežemo na enoto GPIO. Predstavljena je priprava orodij za programiranje 32-bitnega RISC V procesorja in izdelava demonstracijskih programov. Programi uporabijo GPIO enote, PWM izhod in zunanjo prekinitveno linijo s pripravljenimi perifernimi vezji in s tem pokažejo uporabnost in zmogljivost procesorja.

• Language: Slovenian
• Keywords: RISC V, FPGA, NEORV32, programirljivo vezje, periferna enota, RISC, rv32i
• Work type: Bachelor thesis/paper
• Organization: FE - Faculty of Electrical Engineering
• Year: 2022
• PID: 20.500.12556/RUL-138146
• COBISS.SI-ID: 115101955
• Publication date in RUL: 12.07.2022

Secondary language

• Language: English
• Title: Implementation of processor RISC V on programmable device

Abstract

The thesis describes the implementation of a RISC V microprocessor on a programmable circuit. We observed the complexity of the process, the characteristics of the processor and the connectivity of the peripheral units. For implementation, we chose the NEORV32 open-source processor, which has a pre-prepared circuit model for installation on the DE0-Nano FPGA development board. The NEORV32 processor was chosen due to the current RISC V architecture, good documentation and relatively simple structure in the VHDL language, which allows insight into the processor’s operation. We synthesize the processor model using the Intel Quartus Prime tool, where we use a pre-prepared template for implementation. The peripheral circuit is built on a prototype board, which enables easy modification when changing components. The circuit consists of 5 keys, one of which is intended for an external interrupt line, 4 LEDs, a matrix keyboard and a module for converting the UART protocol to the USB protocol. As an example of a complex peripheral component, we present the connection of an expansion board with an interface in the VHDL language, which is connected to a GPIO unit. The preparation of tools for programming a 32-bit RISC V processor and the creation of demonstration programs are presented. Programs use the GPIO units, PWM output and external interrupt line with ready-made peripheral circuits, thereby demonstrating the usability and performance of the processor.

• Keywords: RISC-V, FPGA, NEORV32, programmable circuit, peripheral unit, RISC, rv32i