Implementacija nevronske mreže v vezju SoC FPGA

Marolt, Blaž (author), Šter, Branko (mentor)

V magistrskem delu smo implementirali nevronsko mrežo, sposobno uče\-nja z algoritmom vzvratnega razširjanja napake v programirljivem vezju FPGA. Delovanje nevronske mreže smo testirali na razvojni ploščici Zybo podjetja Digilent. Uporabljena razvojna ploščica vsebuje integrirano vezje Zynq-7000, ki poleg FPGA-dela vsebuje tudi procesor, ki smo ga uporabili za nadzor delovanja nevronske mreže in prenašanje podatkov učne množice. Nevronska mreža lahko izkorišča visoko stopnjo paralelnosti, saj izračuna celotno plast nevronov hkrati. Analizirali smo porabo virov in hitrost delovanja nevronske mreže ter komunikacije med FPGA in procesorskim delom. Slabost omenjenega pristopa je v relativno visoki porabi virov.

• Language: Slovenian
• Keywords: Nevronska mreža, FPGA, Sistem na čipu
• Work type: Master's thesis/paper
• Typology: 2.09 - Master's Thesis
• Organization: FRI - Faculty of Computer and Information Science
• Year: 2021
• PID: 20.500.12556/RUL-131088
• COBISS.SI-ID: 80889603
• Publication date in RUL: 22.09.2021

Secondary language

• Language: English
• Title: Neural network implementation in a SoC FPGA circuit

Abstract

In the master's thesis, we implemented a neural network capable of learning with the backpropagation algorithm in an FPGA integrated circuit. The neural network was tested on a Zybo development board from Digilent. In addition to the FPGA part, integrated circuit Zynq-7000 also contains a processor, which we used to control the neural network and to load the training data. The neural network can take advantage of a high level of parallelism, due to processing of the entire layer of neurons simultaneously. We analyzed the resource consumption and speed of the neural network operation, as well as the communications between the FPGA and the processor part. The disadvantage of this approach is a relatively high consumption of resources.

• Keywords: Neural network, FPGA, System on chip