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Dinamični model električnega pogona na FPGA arhitekturi
ID FURLANI, TAN (Author), ID Fišer, Rastko (Mentor) More about this mentor... This link opens in a new window

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Abstract
V magistrskem delu je predstavljena zasnova nelinearnega simulacijskega modela električnega pogona blagega hibrida podjetja Mahle d.o.o. Model mora biti kompatibilen za generacijo strojne kode, s katero lahko konfiguriramo FPGA. To pomeni, da je primeren za izdelavo HIL simulatorja, s katerim bo mogoče preverjanje delovanja nizkonapetostnih krmilnih naprav. Uvodni poglavji nas uvedeta v obravnavano tematiko, navedeta ključne razloge za uvedbo nove oblike testiranja naprav ter njegove prednosti. Razložita tudi princip delovanja testov in primer, na katerem temelji pričujoče zaključno delo. V naslednjem poglavju opišemo sistem naprav, ki ga želimo simulirati. njegovo delovanje ter matematično opišemo sistem s pomočjo fizikalnih zakonov. Četrto poglavje predstavi izdelavo zveznega simulacijskega modela sistema v programskem okolju Simulink. Pri zasnovi motorja opišemo tudi obdelavo nelinearnih podatkov iz FEM analize, ki jih nato vključimo v model. Na koncu poglavja so predstavljeni še poteki simulacije izdelanega zveznega modela. V petem poglavju opišemo optimizacijske postopke, kot so digitalizacija količin ter diskretizacija simulacijskega časa, ki so potrebni za kompatibilnost modela za generiranje strojne kode, s katero lahko programiramo FPGA. Model simuliramo ter poteke primerjamo z zveznim modelom. V nadaljevanju pokažemo potek generacije VHDL kode iz modela ter omejitve pri tem postopku. Generirano kodo naložimo na FPGA ploščo ZedBoard in preverimo njeno delovanje. V zaključni besedi ocenimo uspešnost pridobljenih rezultatov ter opišemo nadaljnje delo.

Language:Slovenian
Keywords:modeliranje, HIL testiranje, nelinearni dvoosni model, strojna koda, FPGA.
Work type:Master's thesis/paper
Organization:FE - Faculty of Electrical Engineering
Year:2020
PID:20.500.12556/RUL-124077 This link opens in a new window
Publication date in RUL:24.12.2020
Views:1281
Downloads:253
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Secondary language

Language:English
Title:Dynamic model of electrical drive on FPGA architecture
Abstract:
The master's thesis presents the development of a nonlinear simulation model of the electric drive, which will be embedded in mild hybrid drive system manufactured by company Mahle d.o.o. The model shall be compatible with the hardware code generation, which can be used for configuring FPGA logic. That means, it shall be suitable for development of HIL simulator, which can be used to verify the operation of low-voltage control devices. The introductory chapters describe the topic, state the key reasons for the introduction of a new form of testing and its advantages. The principle of test operation and the example on which the presented final work is based, is also explained. Next chapter defines physical system and its operation. It also mathematically describe the system, with the help of physical laws. The fourth chapter presents the design of continuous simulation model in the Simulink software environment. It also describe the processing of nonlinear data from FEM analysis in motor development, which is then included in the model. At the end of the chapter, the simulation results are presented. In the fifth chapter, optimization procedures, such as digitization of quantities and discretization of simulation time are described. These procedures are necessary for the compatibility of model for generating hardware description language code from model, which can be used to program the FPGA. At the end of the chapter, optimised model is simulated and the results are compared with the continuous model. In the following, the VHDL code generation from the model and present limitations of this procedure are presented. Generated code is then loaded on the ZedBoard FPGA board, to check its regularity. In the conclusions, we evaluate the success of the obtained results and describe further work.

Keywords:modelling, HIL testing, nonlinear two-axis motor model, hardware description code, FPGA.

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