izpis_h1_title_alt

Generično vzporedno in sekvenčno digitalno sito na merilni napravi STEMlab
ID KOKALJ, JERNEJ (Author), ID Trost, Andrej (Mentor) More about this mentor... This link opens in a new window

.pdfPDF - Presentation file, Download (2,07 MB)
MD5: 37EE69BD8CF9A6D624B0406C39129A93

Abstract
Signali so v digitalnem svetu zelo pomembni, saj z njimi prenašamo informacije med različnimi sistemi, nadzorujemo različne protokole, delovanja sistemov, izvajamo različne operacije itd. Da pa lahko ti sistemi normalno delujejo, morajo biti ti signali primerno obdelani, idealno brez šuma, velikokrat pa tudi pretvorjeni v drug sporazumevalni protokol. V ta namen sem na vezju FPGA Zynq, ki je del merilne naprave STEMlab oz. Red Pitaya, implementiral kompleksno generično vzporedno in sekvenčno digitalno sito FIR. Z implementiranim modulom lahko uporabnik preko enostavne aplikacije, ki se sporazumeva z napravo STEMlab, določa parametre delovanja, s katerimi se mu ni potrebno podrobneje seznaniti. Arhitektura modula je načrtovana z namenom izrabe vseh strojnih gradnikov tudi v primerih, ko je vzorčevalna frekvenca manjša od sistemske frekvence. S to arhitekturo je v vezju FPGA združena prednost paralelnosti struktur in sekvenčne obdelave signalov, ki smo je vajeni v klasični mikroprocesorski arhitekturi.

Language:Slovenian
Keywords:STEMlab, FPGA, Red Pitaya, Zynq, vzporedno in sekvenčno digitalno sito, digitalno sito FIR, DSP
Work type:Master's thesis/paper
Organization:FE - Faculty of Electrical Engineering
Year:2018
PID:20.500.12556/RUL-100692 This link opens in a new window
Publication date in RUL:06.04.2018
Views:1976
Downloads:720
Metadata:XML RDF-CHPDL DC-XML DC-RDF
:
Copy citation
Share:Bookmark and Share

Secondary language

Language:English
Title:Generic parallel and sequential digital filter on STEMlab measurement device
Abstract:
Signals are very important in the digital world, because we exchange information between different systems, we monitor various protocols, operate systems, perform various operations, etc. However, in order for these systems to function normally, these signals must be properly processed, ideally without noise, and often converted into another communication protocol. For this purpose, I implemented complex parallel and sequential FIR digital filter on the Xilinx FPGA Zynq, part of the Red Pitaya platform. With a simple application that communicates with STEMlab - Red Pitaya the user can specify the operating parameters without in-depth knowledge of the field of signal processing. The module's architecture is designed to efficiently use FPGA resources even in situations when sampling frequency is lower than system frequency. With this architecture the parallel structure capable with FPGA and sequential structure used commonly in microprocessors are combined in one module.

Keywords:STEMlab, FPGA, Red Pitaya, Zynq, parallel and sequential FIR digital filter, FIR digital filter, DSP

Similar documents

Similar works from RUL:
Similar works from other Slovenian collections:

Back