Signals are very important in the digital world, because we exchange information between different systems, we monitor various protocols, operate systems, perform various operations, etc. However, in order for these systems to function normally, these signals must be properly processed, ideally without noise, and often converted into another communication protocol. For this purpose, I implemented complex parallel and sequential FIR digital filter on the Xilinx FPGA Zynq, part of the Red Pitaya platform. With a simple application that communicates with STEMlab - Red Pitaya the user can specify the operating parameters without in-depth knowledge of the field of signal processing. The module's architecture is designed to efficiently use FPGA resources even in situations when sampling frequency is lower than system frequency. With this architecture the parallel structure capable with FPGA and sequential structure used commonly in microprocessors are combined in one module.
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