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Večkanalni signalni generator na merilni napravi STEMlab
ID MAVSAR, MATIJA (Author), ID Trost, Andrej (Mentor) More about this mentor... This link opens in a new window

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Abstract
Za razvoj in raziskovanje je na področju elektrotehnike potrebna natančna in zmogljiva merilna oprema. Naprava STEMlab podjetja Red Pitaya združuje osciloskop in signalni generator z možnostjo programiranja FPGA vezja ter procesorja, s čimer je mogoče napravo prilagoditi zahtevam uporabnika. Signalni generator je v osnovi omejen na dva kanala, zato smo ga želeli nadgraditi in število kanalov povečati. V magistrski nalogi je opisan postopek priprave naprave in spreminjanja kode na različnih nivojih. Uspešno smo implementirali poljubno število kanalov, omogočili aritmetične operacije med njimi in tudi dodali možnost izbire vhodnih signalov kot operandov. Spremembe smo implementirali na nivojih strojno opisnega jezika, API vmesnika in SCPI strežnika (jezika C ter Python).

Language:Slovenian
Keywords:STEMlab, signalni generator, FPGA, SystemVerilog
Work type:Master's thesis/paper
Organization:FE - Faculty of Electrical Engineering
Year:2018
PID:20.500.12556/RUL-100568 This link opens in a new window
Publication date in RUL:29.03.2018
Views:1325
Downloads:545
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Secondary language

Language:English
Title:Multichannel signal generator on STEMlab measurement device
Abstract:
Precise and efficient measuring equipment is required for development and research in the field of electrical engineering. The Red Pitaya STEMlab device includes an oscilloscope and a signal generator with programmable FPGA and processor so the device can be adapted to the requirements of the user. The signal generator is originally limited to two channels, therefore we wanted to upgrade it and increase the number of channels. This master’s thesis describes the process of preparing the device and changing the code at various levels. We successfully implemented an optional number of channels, included arithmetic operations between them, and also added the option of selecting the input signals as operands. We implemented the changes at the levels of hardware description language, API interface and SCPI server (languages C and Python).

Keywords:STEMlab, signal generator, FPGA, SystemVerilog

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