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A systematic approach to configurable functional verification of HW IP blocks at transaction level
Nahtigal, Tomaž (Author), Puhar, Primož (Author), Žemva, Andrej (Author)

URLURL - Presentation file, Visit http://dx.doi.org/10.1016/j.compeleceng.2012.05.006 This link opens in a new window
Language:English
Keywords:digitalna vezja, opis TLM, verifikacija vezij, digital circuits, TLM description, circuit verification
Work type:Not categorized (r6)
Tipology:1.01 - Original Scientific Article
Organization:FE - Faculty of Electrical Engineering
Year:2012
Number of pages:str. 1513-1523
Numbering:Vol. 38, no. 6
UDC:621.3:004
ISSN on article:0045-7906
DOI:10.1016/j.compeleceng.2012.05.006 Link is opened in a new window
COBISS.SI-ID:9324116 Link is opened in a new window
Views:409
Downloads:204
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Record is a part of a journal

Title:Computers & electrical engineering
Shortened title:Comput. electr. eng.
Publisher:Pergamon Press
ISSN:0045-7906
COBISS.SI-ID:577557 This link opens in a new window

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