20.500.12556/RUL-72448 Vmesnik PCI Express na FPGA napravi z uporabo delne rekonfiguracije vezja PCI Express interface on FPGA device with partial circuit reconfiguration Diplomska naloga obravnava razvoj PCI Express vodila na FPGA čipu, kateri ima zaradi uporabe DMA enote visoko hitrost prenosa podatkov. Pri razvoju strojne opreme za pospeševanje obdelave in zgoščevanja podatkov je velik del problema, ki ga je potrebno rešiti to, kako bomo podatke dovolj hitro dostavljali strojni opremi, da se nam razvoj le-te sploh obrestuje. Večina vodil, ki se uporablja za komunikacijo med mikroprocesorji je za ta namen neuporabna, saj so hitrosti prenosa podatkov zelo nizke. Sam sem se odločil za razvoj PCI Express vodila prve generacije, saj nam to vodilo nudi zelo visoko prepustnost, do 250 MB/s na povezovalni pas v vsako smer. Vsaka naslednja generacija prepustnost podvoji, hkrati pa ohranja enak način delovanja, zato je tudi kompatibilna s prejšnjimi generacijami vmesnika. Pozitivna lastnost tega vodila je tudi to, da je trenutno najbolj razširjeno notranje vodilo v računalnikih. Vmesnik sem implementiral s pomočjo Xilinx Virtex 5 FPGA čipa, kateri se je nahajal na XUPV5 razvojni plošči. Moja implementacija je zaradi omejitev razvojne plošče uporabljala samo en povezovalni pas. Na razvojni plošči je nameščen tudi DDR2 SDRAM pomnilnik, katerega sem uporabil za vmesno hranjenje podatkov, katere se bo obdelovalo. V delu se najprej posvetimo osnovam PCI Express vodila, od razlik s predhodniki, preko zgradbe na strojnem in programskem nivoju, razloženo pa je tudi delovanje vodila. Nato si pogledamo tudi delovanje DDR2 SDRAM pomnilnika, na koncu pa predstavim zgradbo in delovanje implementiranega PCI Express vmesnika skozi vse faze razvojnega postopka, prav tako pa je predstavljen tudi razvoj in delovanje Linux gonilnika za PCI Express vmesnik ter testne aplikacije. This thesis describes development of a PCI Express bus on an FPGA chip, which has a very high data throughput when using DMA transactions. When developing hardware for accelerating data compression or data processing, one of the bigger problems is how to get the data to the co-processor hardware fast enough, that the development of such hardware is even reasonable. Most buses, used for communication between processor, are useless for this kind of application, because of low data throughhput. I decided to develop the PCI Express interface of first generation, because this bus offers very high throughput, up to 250 MB/s per lane in each direction. Every following generation doubles the data throughput, while maintaing the same mode of operation, which also ensures compatibility through different generations of interfaces. Another positive feature of the PCI Express bus is also, that it is currently the most common internal interface in modern computers. My interface is implemented using Xilinx Virtex 5 FPGA device on XUPV5 development board. My implementation used only one lane, because of hardware limitations on the development board. The development board also features a DDR2 SDRAM memory, used for intermediate storage of data to be processed. In this thesis we first explain the basics of PCI Express bus, starting with the differences between its predecessors, through different layers of hardware and software, and the inner operations of this bus. Then we look at the operation of DDR2 SDRAM memory and finally, we introduce the structure and operation of my implemented PCI Express interface, through all stages of the hardware development process, ending with presentation of development and operations of Linux device driver and test application for this PCI Express interface. PCI Express vodilo DDR2 SDRAM pomnilnik FPGA Linux gonilnik DMA prenos delna rekonfiguracija PCI Express bus DDR2 SDRAM memory FPGA Linux device driver DMA transfer partial reconfiguration. true false false Slovenski jezik Angleški jezik Diplomsko delo/naloga 2015-09-18 10:00:03 2015-09-18 10:00:10 2022-08-01 16:01:20 0000-00-00 00:00:00 2015 0 0 0000-00-00 NiDoloceno NiDoloceno NiDoloceno 0000-00-00 0000-00-00 0000-00-00 1970-01-01 32361 Kojek_Gasper_-_Vmesnik_PCI_Express_na_FPGA_napravi_z_uporabo_delne_rekonfiguracije_vezja.pdf Kojek_Gasper_-_Vmesnik_PCI_Express_na_FPGA_napravi_z_uporabo_delne_rekonfiguracije_vezja.pdf 1 42B3D42509527EAB46DC00F2F8B469DA 7db8c409be591e0e8a8925e75474e7543cbba8815d3977e87f42ea887a2ee742 5d5c1b7d-a1ad-11eb-a523-00155dcfd717 20.500.12556/rul/bbbe1530-cd67-4c33-8f05-0be282801ae1 https://repozitorij.uni-lj.si/Dokument.php?lang=slv&id=72487 Fakulteta za elektrotehniko 0 0 0