20.500.12556/RUL-30002 Testiranje naprave za zbiranje blokirnih signalov Testing of the interlock collector device Simulator za testiranje naprave, ki zbira blokirne signale, je narejen v dveh izvedbah. Prva izvedba omogoča testiranje naprave na avtomatiziran način, druga pa na ročni način. Zgradba in delovanje teh dveh verzij je zelo podobna. Največjo razliko občuti uporabnik, ki uporablja uporabniški vmesnik oziroma čelno ploščo simulatorja. Napravo, ki jo želimo testirati, je potrebno priključiti na simulator preko vhodno-izhodnih priključkov FPGA kartice simulatorja, serijski port naprave pa na kontroler, kjer poteka programski del simulatorja. Simulator je implementiran v programskem okolju LabVIEW. Kako bo potekalo avtomatsko testiranje, je določeno v simulacijski datoteki, ki jo operater izbere pred pričetkom simulacije. Simulator je sposoben generirati signale štirih vrst: visok logični nivo, nizek logični nivo, viski pulz, nizek pulz. Razdeljen je na dva dela. Programski del in FPGA del. The purpose of simulator which I made is to generate signals for interlock collector device. Interlock collector device is a device which we want to test. A simulator has two versions. First version enables automated simulations and the second version enables manual simulations. Both versions have similar construction and features. The biggest difference is at the front panel. Tested device is connected on simulator through I/O connector of FPGA card and through serial port. Simulator is implemented with National Instruments software called LabVIEW. We must prepare simulation file before start automated simulation. Simulator can generate four different signals: high pulse, low pulse, high level, low level. Simulator is implemented in two parts. Software and hardware. testirana naprava simulator simulacijska datoteka LabVIEW FPGA SET signali CHECK signali Time Out tested device simulator simulation file LabVIEW FPGA SET signals CHECK signals Time Out true false false Slovenski jezik Angleški jezik Diplomsko delo/naloga 2014-11-06 12:35:01 2014-11-06 12:35:01 2022-08-01 10:58:44 0000-00-00 00:00:00 2014 0 0 0000-00-00 NiDoloceno NiDoloceno NiDoloceno 0000-00-00 0000-00-00 0000-00-00 27804 Bogataj_Janko_-_Testiranje_naprave_za_zbiranje_blokirnih_signalov.pdf Bogataj_Janko_-_Testiranje_naprave_za_zbiranje_blokirnih_signalov.pdf 1 58E040469AD738D45413EBF8732CED28 c749c0670b2471c9e15b8eea7b97a5818a1afc115e476c66fbeffce61532e0f5 5946aa5e-a1a8-11eb-a523-00155dcfd717 20.500.12556/rul/a9cb62ef-9dd0-4f64-bcea-42a16c3ea07a https://repozitorij.uni-lj.si/Dokument.php?lang=slv&id=29997 Fakulteta za elektrotehniko 0 0 0